F. Ante, D. K¨alblein, H. Ryu, U. Kraft, T. Egerer, U. Zschieschang and H. Klauk
The maximum frequency fT at which a field-effect transistor can switch or amplify electrical signals is determined by its transconductance gm and its gate capacitance Cgate, the latter of which has an intrinsic componentCGand a par-asitic componentCpar
fT= gm
2πCgate = gm
2π(CG+Cpar). (21) The transconductance gm is a measure for the response of the drain current (ID) of the transis-tor to changes in the applied gate-source volt-ageVGS. In the linear regime of operation, the transconductance is given by
gm= ∂ID
∂VGS =µ CdielW
L VDS, (22)
where µ is the charge-carrier mobility in the semiconductor, Cdiel is the capacitance of the gate dielectric per unit area, W is the channel
width, L is the channel length, andVDS is the applied drain-source voltage.
Figure 61 schematically shows the areas of the transistor that contribute to the intrinsic gate ca-pacitanceCG(the channel area; marked in red) and to the parasitic capacitance Cpar (the gate-to-contact overlap areas; marked in green). As can be seen, CG is determined by the channel area (W⋅L) and Cpar is determined by the area by which the gate electrode overlaps the source and drain contacts (W⋅2ΔL):
CG=CdielW⋅L; Cpar=CdielW⋅2ΔL, (23) whereLis the channel length andΔLis the gate-to-contact overlap. Thus, the cutoff frequency fTcan be written as follows
fT= µ VDS
2πL(L+2ΔL). (24)
Figure 61: Schematic cross-section and schematic top view of an organic thin-film transistor, showing the areas of the transistor that contribute to the intrinsic gate capacitanceCG(channel area; marked in red) and to the parasitic gate capacitanceCpar(gate-to-contact overlap areas; marked in green).CGis the product of the gate-dielectric capacitance per unit area,Cdiel, and the channel area (W⋅L);Cparis the product ofCdiel and the area by which the gate electrode overlaps the source and drain contacts (W⋅2ΔL).
Equation (24) shows that the cutoff frequency of a field-effect transistor depends on four pa-rameters: The carrier mobility (µ), the applied voltage (VDS), the channel length (L), and the gate overlap (ΔL).
Organic thin-film transistors (TFTs) are field-effect transistors in which the semiconductor is a polycrystalline layer of conjugated organic molecules [1]. Unlike transistors based on in-organic semiconductors, in-organic TFTs can be fabricated at temperatures below the glass tran-sition temperature of common polymers, and hence on flexible plastic substrates [2].
Over the past 25 years, the carrier mo-bility of organic TFTs has been improved from 10−5cm2/Vs to about 1 cm2/Vs, mainly through the development of novel conjugated organic semiconductors, better purification of the compounds, and improvements in the thin-film morphology. Although these developments continue, it is unlikely that mobilities substan-tially above 1 cm2/Vs will become common-place in organic TFTs. Also the voltage at which the TFTs are operated is usually dictated by the supply voltage of the integrated system (usually the battery voltage) and thus cannot be easily increased beyond a few volts.
Realistic improvements in the cutoff frequency of organic TFTs therefore require that the chan-nel lengthL and the gate overlap ΔL be made as small as possible. In Fig. 62 the cutoff fre-quency calculated from Eq. (24) is plotted as a function of L and ΔL for µ= 1 cm2/Vs and
VDS= 3 V. The enormous benefit of even mod-est reductions in the lateral TFT dimensions L andΔLis clearly seen.
Figure 62: Cutoff frequency calculated from Eq. (24) plotted as a function of the channel lengthL and the gate-to-contact overlapΔLfor a charge-car-rier mobility of 1 cm2/Vs and a drain-source volt-age of 3 V. The benefit of reducing the lateral TFT dimensionsLandΔLis clearly seen.
Organic TFTs with channel lengths and gate overlaps down to about 20µm can be easily fab-ricated by patterning the gate electrode and the source and drain contacts using commercially available shadow masks [3] that are made by cutting openings into a thin polyimide film us-ing a laser. The various layers of the TFTs are then patterned simply by evaporating the mate-rials (aluminum for the gate electrodes, conju-gated molecules for the semiconductor, gold for the source and drain contacts) through the open-ings in the mask onto a suitable substrate.
Figure 63: Photographs of a polyimide shadow mask and of a shadow-mask-patterned organic TFT with a channel length and gate overlap of 20µm, and current-voltage characteristics of the TFT.
Figure 63 shows a photograph of a polyimide shadow mask, a photograph of a shadow-mask-patterned organic TFT with a channel length and gate overlap of 20µm, and the current-voltage characteristics of the TFT. The gate di-electric is a combination of≈3 nm thick AlOx (obtained by briefly exposing the Al gate to an oxygen plasma) and a≈2 nm thick alkylphos-phonic acid self-assembled monolayer (SAM) formed spontaneously on the AlOx surface from a 2-propanol solution. The capacitance of the ≈5 nm thick AlOx/SAM gate dielec-tric is 0.8µF/cm2. The charge carriers in the organic semiconductor (dinaphtho-thieno-thiophene, DNTT) have a mobility of about 1 cm2/Vs.
According to Eq. (24), the maximum frequency expected for the TFT shown in Fig. 63 is about 40 kHz (L=ΔL= 20µm, µ= 1 cm2/Vs, VDS= 3 V), which corresponds to a signal delay (τ ) of 12.5µsec (2τ= 1/ f). To verify this pre-diction we have fabricated ring oscillators based on TFTs like the one shown in Fig. 63 on a flex-ible plastic substrate and measured the signal
delay of the ring oscillators. For a supply volt-age of 3 V we have measured a signal delay of 30µsec, which is reasonably close to the theo-retically predicted value of 12.5µsec.
The resolution of polyimide shadow masks can be enhanced down to about 10µm [4], but not beyond that. To fabricate organic TFTs with a channel length and gate overlap be-low 10µm we have recently begun to employ high-resolution silicon stencil masks that have been developed and are fabricated at the Institut f¨ur Mikroelektronik Stuttgart (IMS Chips). The stencil masks are produced by etching open-ings (defined with high precision and excellent reproducibility by electron-beam lithography) into a 20µm thick silicon membrane that is sup-ported by a silicon-on-insulator (SOI) wafer [5].
Silicon stencil masks were initially conceived for ion-projection lithography [6], but it turns out they are also useful to pattern the various layers of organic TFTs, with significantly better resolution than what is possible with polyimide shadow masks.
Figure 64: Photograph and a scanning electron microscopy (SEM) image of a silicon stencil mask, pho-tograph of a stencil-mask-patterned TFT with a channel length of 1µm and a gate overlap of 5µm, and current-voltage characteristics of the TFT.
Figure 64 shows a photograph and a scanning electron microscopy (SEM) image of a silicon stencil mask designed and fabricated in col-laboration with IMS Chips, a photograph of a stencil-mask-patterned TFT with a channel length of 1µm and a gate overlap of 5µm, and the current-voltage characteristics of the TFT.
The functional materials of the TFT, including the gate dielectric (AlOx/SAM) and the organic semiconductor (DNTT), are the same as for the TFT in Fig. 63.
Based on the lateral dimensions (L= 1µm, ΔL= 5µm) and the charge-carrier mobility (µ= 1 cm2/Vs), a cutoff frequency of 4 MHz (corresponding to a signal delay of 125 nsec) is expected for this transistor atVDS= 3 V. The signal delay we have measured on ring oscil-lators fabricated using high-resolution stencil masks is 300 nsec at 3 V [7], which is again rea-sonably close to the predicted value of 125 nsec.
Figure 65: Literature overview of signal delays re-ported for organic TFTs in the literature since 1995 (blue data points), and our data (red data points) ob-tained using polyimide shadow masks (L= 20µm) and using silicon stencil masks (L= 1µm).
Figure 65 provides an overview of signal de-lays that have been reported for various or-ganic TFT technologies in the literature since
1995 (blue data points). The signal delays we have measured for our polyimide shadow-mask technology (L=ΔL= 20µm) and our silicon-stencil-mask technology (L= 1µm, ΔL= 5µm) are shown for comparison (red data points). As can be seen, reducing the feature size of the TFTs from 20µm down to a few microns im-proves the dynamic performance of the transis-tors by two orders of magnitude.
References:
[1] Klauk, H.Chemical Society Reviews39, 2643–2666 (2010).
[2] Sekitani, T., U. Zschieschang, H. Klauk and T. Someya.Nature Materials9, 1015–1022 (2010).
[3] Zschieschang, U., F. Ante, M. Schl¨orholz, M. Schmidt, K. Kern and H. Klauk.Advanced Materials22, 4489–4493 (2010).
[4] Zschieschang, U., T. Yamamoto, K. Takimiya, H. Kuwabara, M. Ikeda, T. Sekitani, T. Someya and H. Klauk.Advanced Materials22, 982–985 (2010).
[5] Butschke, J., A. Ehrmann, B. H¨offlinger, M. Irmscher, R. K¨asmaier, F. Letzkus, H. L¨oschner, J. Mathuni, C. Reuter, C. Schomburg and R. Springer.
Microelectronic Engineering46, 473–476 (1999).
[6] Gross, G.Journal of Vacuum Science & Technology B15, 2136–2138 (1997).
[7] Ante, F., F. Letzkus, J. Butschke, U. Zschieschang, K. Kern, J. N. Burghartz and H. Klauk.IEEE International Electron Devices Meeting, Technical Digest p. 516, San Francisco (2010).