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LSI CHIP ME16

Im Dokument 306 ))2 (Seite 62-66)

SECTION 4 THEORY OF OPERATION

50 MILLISECONDS FOR DOUBLE LINE FEE~ OPTION

4.9 POWER SUPPLIES

4.10.2 LSI CHIP ME16

fiCWI-DCWS

(Strobe Counter Outputs)

Generated on LSI chip ME16 pinos 12 (DCW1), 13 (DCW2), 14 (DCW3), 15 (DCW4) and 16 (DCW5). The strobe counter which is internal to the chip is reset by an internal DCWO signal. DCWO, which normally represents the space interval between characters, is generated by either a Prime condition or by DCW5.

During normal character printing, each video STROBE pulse increments the counter~ During elongated character printin g, every alternate STROBE increments the coutner, making each DCW interval twice its normal width.

If the special timing option SPCG is used (which consists of cutting the etch between pin 6 of ME16 and ±OV), then the DCW1-DCW5 signals at the output pins of the chip are encoded from the internal DCW1-DCW5 signals as follows:

External Signal DCW1

Encoded from

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Internal Signals DCWl + DCW3 + DCW5

External Signal DCW2

DCW3 DCW4 DCWS

Encoded from

DCWOI-DCW04 (Delayed Strobe Outputs)

Internal Signals DCWI + DCW3 + DCWS DCW4 + DCWS

DCW4 DCWS

Generated on LSI chip ME16 pins 7 (DCWOl), 8 (DCW02), 9 (DCW03), and 10 (=DC=W-0~4). The delayed strobe counter like the strobe counter is reset by DCWO.

During normal printing of 9 x 7 characters, each DLYSTB pulse in-crements the counter. During elongated character printing, alternate STROBE pulses increment the counter making each DCWO interval twice its normal width.

As in the strobe counter timing, if option SPCG is used, then the

external DCWOI-DCW04 signals are related to the internal DCWOl to DCW05 intervals as follows:

External Signal DCWOl DCW02 DCW03 DCW04 ROME2 (ROM Timing)

Encoded from Internal Signal DCWOl + DCW03 + DCW05 DCW02 + DCW03

DCW04 + DCW05 STROBE + DCW)

Generated on LSI chip ME16 pin 24. This signal is the timing input to the "half-step" character generator ROM (Read-Only Memory).

During normal printing of 9 x 7 characters, each DLYSTB, (Delayed Strobe) pulse generates a ROME2 pulse. When printing elongated 9 x 7 characters, each video STROBE pulse generates a ROME2 pulse.

OSC (Oscillator Output)

Generated on LSI chip ME16, pin 25. The frequency of this system clock is 100 KHz (min.) to 200 KHz (max.). Signal OSC is inverted by ME20-6 to generate OSCXT to the interface connector. Signal OSC is also used by both LSI chips to generate clocks 01 to 02 used internally by the LSI chips.

CLKTB2 (Clock Shift Register Pulse)

Generated on LSI chip ME16 pin 36. This active high pulse is gen-erated by any of the following three conditions:

1. During a prime condition, to load the du-my character into memory - At the end of the PRIME interval, Recirculate signal SRCL goes high and a single CLKTB2 pulse is generated. This forces a single ONE into bit 8 of that shift register location, forming the dummy character.

2. During character printing, to shift the characters out of memory -Each STROBE pulse occurring during Strobe Counter interval DCWO (internal to LSI chip MEI6) generates a CLKTB2 pulse. This shifts the next character to the output of the shift register where it remains until the next STROBE DCWO interval.

3. During the interval following the reception of a carriage return code - A low DSCR input to the chip ANDed with TB8 to allow each 02* clock to generate a CLKTB2 pulse.

CIPX

(Forward Clutch)

Generated on LSI chip ME16 pin 30. This active low output is used to turn on the forward clutch when the printer is ready to print the received line of data.

Signal C!PX goes low when the internal CIPF latch is set. CIPF gets set under the following conditions: (1) the printer is not being primed (PRIME), (2) the right limit switch is not activated (EOPSW), (3) a control character is not detected at the memory output (TB6 or TB7), (4) the left limit switch is activated (RTPSW), and (5) the dummy character is detected at the memory output (TB8). The internal CIPF latch then remains set either until the right limit switch is reached (EOPSW) or a control character appears at the memory output (TB6.TB7). Normally, this control character would be a carriage return code (octal 015). However, if the DSC option is used (jumper EI0 to Ell), the control character could be a carriage return (015), line feed (012), vertical tab (013), or form feed (014) code.

*02 is a phase clock internal to LSI chip MEI6. The frequency of this 02 clock is the same as the OSC output from LSI MEI6.

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SRCL (Shift Register Recirculate Input)

Generated on LSI chip ME16 pin 38. A high SRCL signal along with a single CLKTB2 pulse is generated at the end of each PRIME interval.

This clocks a dummy character into the shift register.

ID

(Light Detect)

Generated on LSI chip ME16 pin 17. Signal LD is normally high indicating no error in the video circuit. However, if the print head travels from the left limit switch (RTPSW) to the right limit switch (EOPSW) with no STROBE pulse generated by the timing fence, then a latch is set within the chip causing LD to go low. This indicates an error

condition. The internal LD latch can be reset only be de-selecting the printer.

PRIME (Prime)

Generated on LSI chip ME16 pin 37. PRIME goes active high for 100-500 milliseconds during a Power Prime (PWRPRM) and approximately 100-400 microseconds during any of the following conditions:

(1) A low DCPRM input from LSI chip ME25,

(2) The printer has just been selected (a low SLCT input to LSI chip ME16) and the Delete Inhibit (DELINH) option is not used

(jumper E14 to E15 is not connected),

(3) A line of data has just been printed (CIPX out of LSI chip ME16 has just gone high).

Prime initializes the printer logic, resets the shift register and loads a dummy character.

CSBSY (Cause Busy)

Generated on LSI chip ME16 pin 35. CSBSY goes active low when a dummy character (TB8) is detected at the shift register output and a Prime operation is not in progress. This condition indicates that the 80th char-acter has just been loaded into the shift register (without a carriage re-turn code). The low CSBSY signal then generates a low BUSY output from LSI chip ME25.

SECTION 5

REMOVAL, REPLACEMENT AND ADJUSTMENT PROCEDURES*

5.1 INTRODUCTION

This section describes the operation, removal/replacement and

adjustments (if required) for each major mechanical assembly in the printer.

Im Dokument 306 ))2 (Seite 62-66)