Low-level interrupt handling

The PIes are initialized by sea UNIX to respond to either edge-triggered or level-edge-triggered interrupts, depending on the capabilities of the machine architecture. The ISA architecture requires that peripherals generate edge-triggered interrupts, but the Me architec-ture requires that peripherals generate level-triggered interrupts.

unsigned char intpri[]

Figure 4.4 Interrupt tables.

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How interrupts arrive in a device driver 83

Level-triggered interrupts are more reliable, as the PIC is less likely to be triggered by noise on the IRQ line and trigger timing accuracy is not so critical. master PIC through IRQ line 7 on the slave PIC. The vector is used to index the Interrupt Descriptor Table (lOT), a table of task gates, interrupt gates and trap gates which indirectly point to the kernel's exception and interrupt handling routines. lOT entries 0 through 63 are all trap gates, except for entry 2 (an interrupt gate to deal with non-maskable interrupts) and entry 8 (a task gate to deal with Double faults). lOT entries 64 through 79 are all interrupt gates, so that SCO UNIX will handle interrupts in the context of the process that is running at the time of the interrupt.

When any of the devices attached to the PICs wants to interrupt, it raises its IRQ line high. If the bit corresponding to the IRQ line in the PIC's Interrupt Mask Register is 0, the PIC raises the INTR line on the CPU. The CPU examines INTR at the end of each instruction, and if it is set, it will acknowledge the interrupt by lowering the Interrupt Acknowledge (INTA) line. On the next clock cycle, the CPU lowers

INTA again, and the PIC responds by loading the interrupt 10 onto the data bus. The interrupt 10 is read from the data bus by the CPU, and control jumps through the appropriate interrupt gate in the lOT into the kernel's interrupt handler. Figure 4.5 shows the interrupt gate mechanism for an interrupt from IRQ 4 on the Master PIC.

The jump through the interrupt gate causes the CPU to perform several actions before it starts to execute kernel text:

• If the interrupt happens whilst the CPU is executing user code at privilege level 3, the CPU must switch to privilege level 0 to handle the interrupt. It loads a new privilege level 0 stack pointer from the user's TSS, and pushes the old level 3 stack pointer onto the system stack. ⁸

• The EFLAGS register and the instruction pointer are pushed onto the system stack.

• The Interrupt Enable (IF) flag is cleared, so that external interrupts are disabled. This is to prevent the current interrupt handler being interfered with by other interrupts.

• A new instruction pointer is loaded from the interrupt gate, and the CPU starts to execute kernel text.

Offset into kernel text segment IRQ4

(Interrupt ID SS)----+- Interrupt gate

Interrupt descriptor table register (IDTR)

I

-Interrupt descriptor table (IDD

Global descriptor table register

(GDTR)-Kernel text

---.

table (GDT)

Figure 4.5 The i386 interrupt gate mechanism.

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Entry point of interrupt handler

for IRQ4

Kernel text segment

Figure 4.6 shows the contents of the system stack on entry to the kernel's interrupt handler from privilege level 3 (user mode).

Each of the IRQ vectors enters the kernel at a different point - the kernel pushes a dummy error code and the IRQ number onto the system stack,9 and then jumps to a common interrupt handler. The common interrupt handler does the following:

(1) Pushes all of the general purpose registers onto the system stack.

(2) Pushes the DS, ES, FS and GS segment selectors onto the system stack.

(3) Copies the ESP register into the stack-frame base pointer register,

EBP.

(4) Saves the current software priority level on the stack, by copying it into the space occupied by the dummy error code.

(5) Uses the IRQ to index the table of software priorities, intpri, to determine the new software priority level corresponding to the device on this IRQ.

(6) Uses the new interrupt priority level to index the table of PIC masks, iplmask, and writes out the contents to the PICs' Inter-rupt Mask Registers so that interInter-rupts from all devices at this priority or less are disabled.

How interrupts arrive in a device driver 85

SS :ESP (0) from user's TSS

New SS:ESP

--.

..

User's SS: ESP User's EFLAGS

User's CS: EIP System stack in U-area

Figure 4.6 The system stack on entry to the kernel from user mode (privilege level 3).

(7) Sends an End-Of-Interrupt command to the PICs, so that they can now accept further interrupts.

(8) Sets the IF flag so that external interrupts are now enabled again.

Interrupts can now arrive, but only from higher priority devices (see step 6, above).

(9) Pushes the old software priority level onto the system stack.

(10) Pushes the IRQ onto the system stack.

Finally, the IRQ is used to index the table of device driver interrupt routine names, ivect, and control jumps to the device driver's XXintr routine. The IRQ is passed to XXintr, so that if more than one piece of hardware is sharing the same device driver, the device driver can establish which device actually interrupted. For example, COM 1 and COM2 on IRQs 4 and 3 (Figure 4.3) share the same serial I/O device driver:

XXintr(irq) int irq;

Figure 4.7 shows the contents of the system stack on entry to an XXintr routine from user mode (privilege level 3).