LOAD INSTRUCTION OPERATION

11A

Instruction ALU Operation

ALU

Note: On machines without extended addressing, the line 'Byte X Tie Up' (CD003) forces the machine to decode a Load Halfword instruction.

TAR

I

^DF971^DE971

TAR is incremented by two in ALU. This new address is placed in TAR and in the I AR. because of bridge storage characteristics. :~~:~~i:~ DRESS/DATA switches are compared. ~~:i:~:~:

~;l~~li The ADDRESS COMPARE light ~;11~;1;1

I

because of bridge storage characteristics.

DE002 bit card locations.

LOAD INSTRUCTION OPERATION

6-390

~) ,

^f~)'

From Preceding Page

1--

^{Load Only} storage address. If general register 0 (I AR) is specified

Instruction 0 peration

110

^Load ^Add

See Page 6-100.

To Next Column

... _ _ _ _ _ _ _ _ • DE974

_________ S_D_R ________

~IDNOOl

Note: See page 6-000 for data flow bit card locations.

,,(~\

(1) '0" 10

. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ^{0 0 0 0} ⁽⁾ ^{0 0 0}

From Preceding Page

• 12F

3705-1 Only

+- _•

12C

Load Only

+

Load Only

120

To Next Column

Load Only

No Action

12F time is necessary because of bridge storage characteristics.

Constant (+2) - - ,

X Force Constant • _ _ _ _ _ _ _ .. DE971

Instruction Operation

Load Add

See page 6-100.

0002 (C F001 ) DE975 DF975

DG975 ^TAR

I

^{. DG971}^DF971

I

X Gate TAR to Y Bus (CS004) X TO + T1 Time Set

I

^A-B^Reg^(Ceo07) ^X Gate Y Bus to B Reg (CS004)

~

TO + Tl Time Set

I

A-B Reg (CC007) . -_ _ _ _ _ _ _ .. DE002

... _ _ _ _ _ _ _ _ • DE974

I

^DF974

. DG974

L---~I---Se-t-T-A-R---~

Z Register

X I (CS007)

I

^DE971

TAR DF971

L---__ r---~ D G 971 X Gate TAR to Y Bus (CS004)

I

Set SAR (CS007)

.---II1II I

^DE971^DF971

DG971

L-. _________ ~---~

DF002 DG002

I

Load OO'Y

-13A~

1 __

p-- ^~L.

^{_ _ _ _}S_t_o_ra_g_e _ _ _ ...,j

Bytes 0 and 1

13E •

Load Only 13E time is necessary

because of bridge storage characteristics.

+

Load Only

138

To Next Page

,Jl?

Gate SAR To ABu, (CS004)

DE975 DF975

L.... _______________ ~---~DG975 L.... _______________ - - . ____________________ - - I A POD 1

i a t e Mem Byte to M Bu,

I

^(CS005)

X Set SDR Byte (eS007)

I

SDR

DN001

Note: See page 6-000 for data flow bit card locations.

X TO + Tl Time Set

I

^A-BReg (CC007)

X TO + T1 Time Set

I

A-B Reg (CC007) X Gate Y Bus to B

I Reg (CS004)

~---

. . . DE002 DF002

DG002

Instruction Operation DE008

L.-_ _ - . -_ _ ...J D F008 Load Compare

DG008

. . _ _ _ _ _ _ _ IIIIII! DE974

I

^{. DG974}^DF974

Z Register

L.... ____________ ~I

______

- - - l

X Set DR 2 (CS007)

I

~---~

^DE003_DF003

X Gate Displ Reg 2

I

to Ind. (CU001)

I

^AP011

Display B . AP012

See page 6-100.

LOAD INSTRUCTION OPERATION

(PART 3)

6-410

From Previous Page.

1

-13F

t

Load Only

13C

Instruction Load See page 6-100.

To Next Column

" ^~,~) ,tr""

^I\~.;~

(fJI _(t 0\

^\ ^I

Load Only

Operation A Reg Direct

13F time is necessary because of bridge storage characteristics.

I

^DNOOl

SDR

~---~---~

C and Z Latches

x

x I

DE975 DF975 DG975 TO + T1 Time Set A-B Reg ~CC007)

DE975 DF975 DG975

DF008 DG008

Z Register

I

DE974 DF974 DG974 CZOOl

X Write LS (CC006)

0 C C!

^*''''','

^'^'''.,,';^'^'

0 I

General Register (R)

CI~\ 'PI

^~n\\(l-p'" ^I' ^-) '

...

^{' J}

DE002 DF002 DG002

,~~,

(-'I r I

'v I_n, , _{~~

\~j ^\' ⁾

Load Only

130

End of Instruction

,1'-" (""~'

(-,,"1 ""'-.J! ~

j;

DE008 DF008 DGOO8

X Set T AR ~CS007)

I

DE971 TAR

I

^DF971_DG971

I

Gate TAR to Y Bus X

I

^~CS004)

X Set SAR ~CC007)

DE971 SAR

I

^DF971_DG971

Note: See page 6-000 for data flow bit card locations.

in)

l')'1 0,) _("~I

0 ^'\J' ^'",J' ~"~"

I~'\ ^''-Ly' ^,I

I'D

^'1" ^'.'

---~~~., ..

-DE002 DF002 DG002 TO + Tl Time Set A-8 Reg (CC007)

DE974 DF974 DG974

I

DE002 DF002 DG002

I nstructi on Load

Operation B Reg Direct See page 6-100.

Write LS ~CCOO6)

DE002 General Register (lAR) DF002

(n" !fJI ^[r'" :DI ^,f'; it t ^('",

'U

ⁱ ^'-'--j. ^' ^. ^'.,^~^" ^" ^"'l

;v

^[0\^\'ly/

o o ^{0 0} ^{o o} o o o o ^{o o} o o o o o

STORE INSTRUCTION OPERATION

Note: On machines without extended addressing, the line 'Byte X Tie Up' (CD003) forces the machine to decode a Store Halfword instruction.

The address exception checks made during each instruction cycle are not shown. See AlD pages CM002 and CM003. during the first store instruction of a pro· ." TAR is incremented by

two in AlU. This new address is placed in TAR and in the fAR.

11 E time is necessary because of bridge storage characteristics. because of bridge storage characteristics.

Note: See page 6-000 for data flow bit card locations.

X Set SDR Byte

STORE INSTRUCTION OPERATION

o o

6-430

o ^{)

From Preceding Page

1 _ - - - - - - -

--11C 58 ::::::::::SA:x:R:s:e:t:L:A:R::(C:!o:~~;1

Store Only

110

To Next Column

o o

I

~---1111111111

_LAR

I

^DE002^DF002

'--_ _ _ _ _ _ _ _ ... DG002 From Preceding Page

~

^XGate SDR Bits to A Bus (CF003)

r---~---,DE975 , . . _ _ _ _ _ _ _ . . . DE002

Instruction Operation

ST Add

See page 6-100.

o o ^0·'

^, ^,

DE975 DG975 X TO + T1 Time Set

I

A·B Reg (CC007) ^X

I

DF002 DG002

~---~

^DE002

o

~---~----~

)11---([0

DF008 ^E008 ' - - - r - - - - ' DG008

Z Register X Set TAR

I (CS007)

TAR f

DE974 DF974 DG974

DE971 DF971 DG971 X Gate TAR to Y Bus (CS004) x . I Set SAR (CS007)

, . . - - _ - _ ... _-.DE971 DF971 '--_ _ _ _ ..,... _ _ _ _ ~ DG971

o o o o o

DF002 DG002

o o

Store Only

(PART 2)

. . . _ _ _ _ _ _ _ . . . DE002 DF002 DG002 TO + T1 Time Set

I

^{A·B Reg}^(Ceo07)

B Register

DE002 DF002 DG002

fr-1 ___ S_tor_age_~

_ - - - r r D E 0 0 8 DF008 '--_ _ ...--_ _ -' DG008

12A,

To Next Page

o o o

Instruction Operation ST B Reg Direct See page. 6-1 00.

... ---11IIIIIIII

_·1 ^DE974

DF974 . DG974 Z Register

---...-1 ----'

X . Set SDR Byte (CS007)

I

^SDR ^DNOO1

Bvte~ Tt~oand

To. page To Next

_ _ _ _ _ _ _ _ ^~_ _ _ Page _ _ _ _ _ _ _ _ _ _ _ Store Only 12E time is necessary

because of bridge storage characteristics.

Note: See page 6-000 for data flow bit card locations.

o o o o o o o o o o

6-440

o

• ^{o o} ^o ^{o o} ^o ^{o o}

From Preceding Page -stc;'re Only

lililili~~~:~!:~~~~;~:~~;~;~;~~~~;:~:;~;:~~~;~j:~:;~m~~~m~j~jj~~~~~~~~~~~~~~~~t~j~j~~!i!ilili!i

:~:~:~:~ placed in storage. The addresses :~:~:~:~:~

:~:~:~:? in the SAR and in the ADDRESS/DATA ~:~:~:~:~:

iiiiii: ~w~~~e~;~ec~~~~ ~t t~~mes ~i~i~i~i~i

:::::;::: on if the address compare conditions ~:~:~:~:~:

il~l~~~~ are met. (See LOAD/STORE ADDRESS ~~~~~~~~~:

:llllllll~l~~;~;~;l~~;~;ll~;l;;~i~;~M;:;l;i:~:~t:mm::mImf:ml:~::~l~:~:~ilili!llj:

From Preceding Page

o

,

-I I

I

L -_______ S_t_or_a_g_e ______

--Jr- --- ^_J

12B

Instruction Operation

ST Compare

See page 6-1 00.

o o o o

DF971 DG971

o o o o

APOOl TO + Tl Time Set

X XI

A-B Reg (CC007)

I

TO,+Tl Tirpe Set,

A-B'Reg (CC0071' _ _ _ _ _ ---1x_G_a_t_e_Y_BU_s_to B

. I

Reg (CS004)

Z Register

I

DF974 DG974

X Set DR 2 (CS007)

I

DF003 DG003

X Gate Displ Reg 2

I

^{to Ind.}(CUOOll

o o

Store Only

12D

• o o

Instruction

o o

Constant (-2) - - - , X

o o

DF975 DG975

TO + Tl Time Set

r

A-B Reg ICC007!

o o

'111---1(

^DF008

o o o ^o

I

DF971

TAR . DG971

I

X Gate TAR to Y Bus (CS004) X

I

Gate Y Bus to B Reg (CS004) X

I

TO + Tl Time Set A-B Reg (CC007)

DF002 DG002

ST Subtract DG008

See page 6-100.

,-- I

Z Register X

I

Set TAR

I (CS007)

DF974 DG974

I

-OF971

TAR . DG971

I

X Gate TAR to Y Bus (CS004)

I

DF971 DG971

I

To Next Page

-t-- - -

^{' - '}

^-'-

--'-I

Store Only 12F time is necessary because of bridge storage characteristics.

Display B

I

^AP012

_{-.J_'} rEl ^{~ ~}

^Storage

• 12C

Store Only

,--

To Next Column

•

To Next Page

No Action

Note: See page 6-000 for data flow bit card locations.

STORE INSTRUCTION OPERATION (PART 3)

o o

6-450

o o

From Preceding Page

1

-13E 3705.1 Only

Store Only

~

Store Only

From Page 6-440 A

138

Byte X

13E time is necessary because of bridge storage characteristics.

From Preceding Page

,----T

I

^X Gate SAR To A Bus

I

<CS004)

I I I I I I I

DE975 DF975 DG975

X TO + Tl Time Set

I

A-B Reg (CC007)

IJIII---~

^DE975^DF975

DG975

APOOl

X TO + Tl Time Set

I

A-B Reg (CC007) X Gate Y Bus to B

I

Reg (CS004) DE002 DF002 DG002

'--_ _ _ S_to_ra_g_e _ _ _

...a~- ^J )1 _ _ _ _ _ "-0

^E008

Store Only

To Next Col,umn

o o ⁽⁾ o o

r---,---~

Instruction Operation

ST Compare

See page 6-100.

13F time is necessary because of bridge storage characteristics.

o o

DF008 DG008

Z Register

DE974 DF974 DG974

o

X Set DR 2 (CS007)

I

DE003 DF003 DG003

X Gate Displ Reg 2 to Ind. (CU001)

o

AP011 AP012

o ^o o o

13C

• t

Store Only

No Action

Store Only

DE002 DF002 DG002

X TO + Tl Time Set A-8 Reg (CC007)

B Register

DE002 DF002 DG002

ALU

130,

End of Instruction

o

Instruction Operation ST B Reg Direct See page 6-100.

X Set TAR (CS007)

I

DE971 TAR

I

^DF971DG971 Force interrupt

address X'0012' X Gate TAR to Y Bus

during program

I

^(CS004)

level 1 interrupt

(CS004) see page X Set SAR (CS007)

6-270.

I

DE971

SAR DF971

DG971

Note: See page 6·000 for data flow bit card locations.

o o o o o ^o o o

DE974 DF974 DG974

X Write LS (CCD06) DEOD2 DFOO2 General Register (I AR) DG002

o o o o o o

•

The CCU takes an 11 and an 12 cycle to execute either the 'insert char-acter and count' or 'store charchar-acter and count' instructions.

For the 'ICT' and'STCT" instructions, the general register designated by the R field in the instruction must be an odd-numbered register;

therefore, the general register

=

(2xR) +1.

INSERT CHARACTER AND COUNT (ICT)

o

1-3 4 5-6 7 8 9 10 11 12 13 14

I

⁰

I ^B I ^o I

I

^o ^o ^o ^o ^o

The B field specifies a general register in the active group. The register contains an address (effective address) that is used to address storage.

o

The content of the register specified by B is incremented by 1 after the effective address has been obtained. The byte at the effective address is placed in byte 0 (N=O) or byte 1 (N=1) of the general register designated by the R field. The register specified by R must be an odd-numbered register. Register 0 should not normally be specified in the B field because it contains the instruction address.

The

'c'

and

'z'

latches are not changed.

Note: If the registers specified by Band R are the same, the con-tents of byte 1 of the register is incremented before the B-bit char-acter is inserted. If N=l, the inserted charchar-acter then overlays byte 1 of the same register, and the previous incrementing has no significance. If N=O, the character is inserted into byte 0 of the register, and byte 1 con-tains the original value plus 1.

Im Dokument - = . = = - = Communications Controller Theory-Maintenance (Seite 123-131)

11A

I

I

6-390

~) ,

1--

110

~IDNOOl

(1) '0" 10

. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 () 0 0 0

•

12F

+- •

12C

+

120

I

I

I

I

~

I

I

I

I

I

.---II1II I

I

-13A~

1 __

p-- ~L.

13E •

+

138

,Jl?

I

I

I

I

~---

I

______

I

~---~

I

I

6-410

1

t

" ~,~) ,tr""

(fJI (t 0\

I

x

x I

I

0 C C!

*''''','

0

I

CI~\ 'PI

...

'v I_n, , {~~

,1'-" (""~'

j;

I

I

I

I

I

l')'1 0,) ("~I

I'D

I

(n" !fJI [r'" :DI ,f'; it t ('",

'U

;v

o o 0 0 o o o o o o o o o o o o o

STORE INSTRUCTION OPERATION

o o

6-430

. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ^{0 0 0 0} ⁽⁾ ^{0 0 0}

+- _•

p-- ^~L.

" ^~,~) ,tr""

(fJI _(t 0\

^*''''','

'v I_n, , _{~~

l')'1 0,) _("~I

(n" !fJI ^[r'" :DI ^,f'; it t ^('",

o o ^{0 0} ^{o o} o o o o ^{o o} o o o o o

o ^{)

o o ^0·'

• ^{o o} ^o ^{o o} ^o ^{o o}

lililili~~~:~!:~~~~;~:~~;~;~;~~~~;:~:;~;:~~~;~j:~:;~m~~~m~j~jj~~~~~~~~~~~~~~~~t~j~j~~!i!ilili!i

iiiiii: ~w~~~e~;~ec~~~~ ~t t~~mes ~i~i~i~i~i

:llllllll~l~~;~;~;l~~;~;ll~;l;;~i~;~M;:;l;i:~:~t:mm::mImf:ml:~::~l~:~:~ilili!llj:

--Jr- --- ^_J

o o o ^o

^-'-