Lithographic patterning process

In the summer of 1958 Jack Kilby made an important breakthrough in the advancement of transistors and invented the first integrated circuit (IC).¹ This can be seen as the beginning of the modern computer age. Only seven years later the development of the performance of ICs grew so rapidly, Gordon Moore made the prediction that the number of transistors on one IC doubles every two years with decreasing costs per single transistor. This describes the so-called “Moore’s Law” (Figure 1).²

Figure 1: Left: The minimum cost of a single component (transistor) is decreasing with evolution of ICs. Right: The number of components per IC is predicted to be doubled every two years.

Moore was proved right and the development of ICs proceeded as he expected in the following decades. This advancement was mainly attributed to the steady reduction in component’s size. For semiconductor industry his prediction became more and more a kind of

22

business model but also a challenge. As a result companies of semiconductor industry incorporated national and soon international to state their technological needs and to coordinate developments of ICs. This trade association meets every year and reports overall 17 scopes on research directions and suggests their realization timelines up to 15 years summarized in the so-called “International Technology Roadmap for Semiconductors”

(ITRS).³ Such research directions are for instance further miniaturization or the design of transistors, reduced power consumption, and increase in performance. Recently Intel Corporation presented the first demonstration of a 22 nm microprocessor in 2011.⁴ This microprocessor – code-named Ivy Bridge – is the first chip uses 3-D Tri-Gate transistors, which represents a breakthrough in transistor performance and energy efficiency. The realization of such microprocessors is a very complex process and consists of about 500 processing steps.⁵ This large number comes from repeating lithography and etch pattern transfer processes up to forty times. In Figure 2 a simplified pattern transfer process is illustrated.

Figure 2: A simplified illustration of the lithographic and etch pattern transfer process.

At the beginning of this lithographic process the substrate has to be deeply cleaned to remove contaminations and annealed to remove water.⁶ In the following step (1) a silicon oxide layer is created on the silicon wafer. This can be conducted, e.g., by the oxidation of silicon at very high temperatures in the presence of oxygen or by plasma etching. Ongoing an adhesion promoter solution is spin cast on the substrate. The most common used adhesion

1.Deposition of oxide layer on silicon wafer

2.Application of photoresist 3.UV-exposure through shadow mask

4.Development of resist 5.Etch of oxide layer 6.Remove remaining resist

Silicon wafer

Photoresist Oxide layer

Shadow mask UV light

23 promoter is hexamethyl disilazane (HMDS) which reacts chemically with the surface hydroxy groups. In the second step (2) a photoresist solution is spin cast on the substrate for film application. The film thickness must not exceed the aspect ratio of 3:1 in respect to the targeted line width due to certain pattern collapse. The thickness is adjustable out of the concentration of the solution, the photoresist material itself, and the acceleration and the final revolutions per minute (rpm) of the spin casting process. Subsequently the film is annealed for post apply bake (PAB) to remove most of the remaining solvent in the resist film and to stabilize the film. The basic principle of the following exposure step (3) is to generate a change in dissolubility of the resist film for the ongoing development step (4). This is the actual lithographic pattern transfer as the resist film is exposed through a shadow mask. As already mentioned, the whole process is conducted many times in the production of ICs and thus a precise alignment of mask in every exposure step to substrate is required. In the case of high performance resist systems the exposure alone creates no change in solubility. For these systems a subsequent annealing step is necessary, the so-called post exposure bake (PEB). In the exposed areas a photoactive compound is activated and a catalytic reaction takes place during the PEB. For the following development step (4) an aqueous base (usually tetramethyl ammonium hydroxide: TMAH) is used. In this step the base-soluble resist material is dissolved and the pattern – the image of the shadow mask – is left on the substrate. These patterns are annealed in a following postbake to remove residual water or gas, to improve the adhesion, and to harden for withstanding the upcoming harsh etching step (5). In this step the actual purpose of the resist material becomes important: The resist material ‘resists’ the etchant and protects the oxide areas covered by the resist and thus only the unprotected areas are etched. Such etchants are either acid solution or more commonly dry plasma. The last step in this process contains the stripping of the remaining resist material (6). One option to remove the organic material is to use wet chemical as inorganic acid-based systems or phenol-based strippers. Another method – standard in semiconductor processing – is the use of oxygen plasma which can even strip the etched resist material but leaves the inorganic surface untouched. Further steps are, e.g., ion implanting for altering conduct electricity (doping), applying multiple layers of metal (copper) for electrical connections, and implementation of low-κ materials, supplementing the actual patterning transfer process. At the end of all processing steps the finished microprocessor is coated with a so-called passivation layer. This insulating layer increases electrical stability but also protects the IC from contaminations.

24

Each of these processing steps contains process variables like time, concentration, material, temperature, dose, to name but a few. A variation of one variable at the beginning of this multi-variable process often affects negatively the following steps in this extreme sensitive and thus automated procedure. This sensitivity to process conditions and utilized resist material increases with the further miniaturization of ICs and requires the further development and time-consuming optimization of exposure tools, resist materials, additives, and process set-ups.