CHAPTER 3 CPU O PERATION
3.5 Interrupts
Interrupt is a function to process factors, that generate asynchronously with program execution, such as a key entry and an end of a peripheral circuit operation. When the CPU accepts an interrupt request that is sent by the hardware, the CPU stops executing the current sequence of the program and shifts into the interrupt processing. When all the interrupt processing has finished, the interrupted program is resumed.
The E0C63000 has the hardware interrupt function for the peripheral circuits including an NMI (non-maskable interrupt) and the hardware interrupt function. The hardware interrupts excluding the NMI can be set to the DI (disable interrupts) status by setting the I (interrupt) flag.
I flag = "1": EI (enable interrupts) status ...The CPU accepts interrupt requests from the peripheral circuits.
I flag = "0": DI (disable interrupts) status ...The CPU does not accept interrupt requests from the periph-eral circuits. (excluding NMI and software interrupts) The I flag is set to "0" at an initial reset. Furthermore, all the interrupts including NMI are masked and cannot be accepted regardless of the I flag setting until both the stack pointers SP1 and SP2 are set in the program after an initial reset.
3.5.1 Interrupt vectors
Interrupt vectors are provided to execute a interrupt service routine corresponding to the interrupt generated.
The interrupt vectors are assigned to the following addresses in the ROM.
NMI interrupt vector: 0100H
Hardware interrupt vectors: 0101H to 010FH Software interrupt vectors: 0111H to 013FH
Each of the addresses listed above corresponds to an interrupt factor individually. A branch (jump) instruction to the interrupt service routine should be written to these addresses.
Up to 15 hardware interrupt vectors are available, however, the number of vectors is different depending on the E0C63 Family models. The addresses, that are not assigned to the hardware interrupt vector within the addresses 0101H to 010FH, can be used as software interrupt vectors. In addition, since the hardware interrupt service routines can be executed using the software interrupt, up to 63 software interrupts can be used (excluding the address 0110H because it is the program start address).
3.5.2 Interrupt sequence
• Hardware interrupts
Hardware interrupts including NMI are generated by the peripheral circuits. The peripheral circuit that contains the interrupt function outputs an interrupt request to the CPU when the interrupt factor is generated. The NMI terminal for NMI or IRQ terminal for other interrupts goes low. Sampling the NMI signal is done at the falling edge by the CPU. Sampling the IRQ signal is done at the rising edge of the T3 state in the bus cycle. The CPU executes the following process after accepting an interrupt request.
Bus cycle 0 Sampling the interrupt request.
Bus cycle 1 The last execution cycle of the instruction under execution becomes a dummy fetch cycle. This cycle turns the interrupt acknowledge signal low (both NACK and IACK for NMI, IACK only for a normal interrupt), which indicates that the interrupt has been accepted.
Bus cycle 2 Saves the F register into the stack indicated by the SP2, then resets the I flag to "0" to prohibit following interrupts (excluding NMI).
Bus cycle 3 Sets the data bus status DBS1/DBS0 to "01B". Then, turns the vector read signal RDIV low and reads the interrupt vector (4 bits) output from the peripheral circuit to the data bus.
When NMI is generated, this cycle becomes a dummy cycle because the interrupt vector is fixed at 0100H.
The NACK and/or IACK are returned to high at the end of this cycle.
Bus cycle 4 Fetches the instruction in the interrupt vector (data that is read in Bus cycle 3 becomes the low-order 4 bits of the vector) and saves the content of the PC (address immediately after the instruction that is executed in Bus cycle 0 or branch destination address when it is a branch instruction) to the stack indicated by the SP1.
Bus cycle 5 Executes the instruction fetched in Bus cycle 4. (If it is 1-cycle instruction, the next instruction is fetched at the same time.)
• Exceptional acceptance of interrupt
For all the interrupts including NMI that are generated during fetching the following instructions are accepted after the next instruction is fetched (it is executed) even in the EI (enable interrupts) status.
1. Instructions that set the E flag
LDB %EXT,imm8 LDB %EXT,%BA 2. Instructions that write data in the F (flag) register
LD %F,%A LD %F,imm4 AND %F,imm4 OR %F,imm4 XOR %F,imm4 POP %F RETI
These instructions set the E flag or may set it. Therefore, if an extended addressing instruction follows them, it is executed previous to the interrupt processing.
Further, these instructions may modify the content of the I flag. If these instructions set the I flag (EI status), the interrupt processing is done after executing the next instruction. If these instruc-tions reset the I flag (DI status), interrupts generated after the instruction fetch cycle are masked.
3. Instructions that set the stack pointer LDB %SP1,%BA LDB %SP2,%BA
These two instructions are also accepted after fetching the next instruction. However, these instructions must be executed as a pair. When one of them is fetched at first, all the interrupts including NMI are masked (interrupts cannot be accepted). Then, when the other instruction is fetched, that mask is released and interrupts can be accepted after the next instruction is fetched.
CLK
pc-3 pc-1 0100H ANY
2 1 2 ANY
pc
SP2-1 DUMMY SP1-1
F reg. ANY pc
Interrupt processing by the hardware Interrupt sampling
Interrupt sampling Executing the interrupt service routine
Fig. 3.5.2.1 NMI sequence (normal acceptance)
Fig. 3.5.2.2 NMI sequence (interrupt acceptance
ANY ANY DUMMY (0100H) ANY
pc-2 pc-1 0100H ANY
ANY 2 1 2 ANY
Interrupt processing by the hardware Executing the interrupt service routine Interrupt sampling
4–6 cycle
DUMMY
In this chart, the dummy fetch cycle starts after fetching the
"LD %A, [%X]" instruction that follows the "LDB %EXT, imm8" instruction.
CLK PK PL PC FETCH BS16 DBS1/0 WR RD RDIV DA00–DA15 D0–D3 M00–M15 IRQ IACK NACK IF
0 1 2 3 4 5
DUMMY (010xH) ANY
pc-3 pc-1 010xH ANY
2 1 2 ANY
pc
SP2-1 DUMMY SP1-1
F reg. xH
pc
ANY LD %A,[%X]
0 3
ANY
[00xxH]
pc-2 LDB %EXT,imm8
ANY
00xxH
Inte rrupt vector CLK
PK PL PC FETCH BS16 DBS1/0 WR RD RDIV DA00–DA15 D0–D3 M00–M15 IRQ IACK NACK IF
0 1 2 3 4 5
ANY ANY DUMMY (010xH) ANY
pc-2 pc-1 010xH ANY
ANY 2 1 2 ANY
pc
SP2-1 DUMMY SP1-1
ANY
F reg. xH
pc
Interrupt processing by the hardware Executing the interrupt service routine 4–6 cycle
Interrupt sampling
Inte rrupt vector
Fig. 3.5.2.3 Hardware interrupt (IRQ) sequence (normal acceptance)
Fig. 3.5.2.4 Hardware interrupt (IRQ) sequence (interrupt acceptance In this chart, the dummy fetch cycle starts after fetching the
"LD %A, [%X]" instruction that follows the "LDB %EXT, imm8" instruction.
• Software interrupts
The software interrupts are generated by the INT instruction. Time of the interrupt generation is determined by the software, so the I flag setting does not affect the interrupt. That processing is the same as the subroutine that evacuates the F register into the stack.
This interrupt does not change the interrupt control signals between the CPU and the peripheral circuits, or the I flag either. An address that is specified with the operand of the INT instruction is used as it is as the interrupt vector.
CLK PK PL PC FETCH BS16 DBS1/0 WR RD RDIV DA00–DA15 D0–D3 M00–M15 IRQ IACK IF
1 2 3 4 5
ANY ANY INT addr6 (01addr6H) ANY
pc-2 pc-1 01addr6H ANY
ANY 2 3 2 ANY
pc+1 SP2-1 DUMMY SP1-1 ANY
F reg. xH pc+1 pc
DUMMY
Fig. 3.5.2.5 Software interrupt sequence
3.5.3 Notes for interrupt processing
(1) After an initial reset, all the interrupts including NMI are masked and cannot be accepted regardless of the I flag setting until both the stack pointers SP1 and SP2 are set in the program. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set.
(2) The interrupt processing is the same as a subroutine call that branches to the interrupt vector address.
At that time, the F register is evacuated into the stack. Therefore, the interrupt service routine should be made as a subroutine and the RETI instruction that returns the F register must be used for return.
(3) If an interrupt (including NMI) is generated while fetching an instruction, that sets the E flag or writes data to the F (flag) register, the interrupt is accepted after fetching (and executing) the next instruc-tion. Therefore, the extended addressing with the EXT register is processed before executing the interrupt processing. However, if the stack data in the memory is directly changed in the interrupt service routine, the F register in which the E flag is set may return. In this case, the instruction imme-diately after returning by the RETI instruction is executed in the extended addressing mode by the E flag that is set to "1". Pay attention to the F register setting except when describing such a processing consciously.