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8.5 INTERRUPT SERVICE ROUTINES
INPUT/OUTP.UT TECHNIQUES
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When an interrupt occurs the interrupt instruction generally calls an interrupt service routine. This is a subroutine, but it has two special requirements. It must:
a) Preserve the environment.
b) Find out why it was called.
8.5.1 Preserving the Environment
An interrupt service routine does not use the registers to exchange data with a calling program. On the contrary, it must preserve the contents of all registers and flags, and restore those contents before returning to the instruction that was interrupted. The interrupted program module makes no special provisions for the interrupt, and except for the time taken by the interrupt service its functions must not be interfered with. It may be interrupted but not disrupted, and the service
transparent.
routine must be
The first several instructions in any interrupt service routine are almost invariably PUSH instructions to save the registers:
PUSH PSW Save A and flags
The ro~tine c:in now use all of the registers to perform its functions - typi~ally input and/or output. When finished it restores the ehvironment that existed before the interrupt by popping the registtrs in reverse order:
bop
POP I POP I
POP I
EI I RET I
H D B
PSW
Rememblr that the interrupt itself disabled the interrupt system, so I
to reJtore the environment, allowing for another interrupt, there must Je u an EI in the service routine. If this is placed immediately before
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the return, it is guaranteed that the return will be execut~d. Pla.cing it earlier in the interrupt routine will allow [ another interrupt to interrupt the interrupt routine! This is somJtimes done, but usually with priority interrupt systems (which are di\scussed below), and requires special consideration. Many interrJpt service routines cannot tolerate being interrupted. This is the case with the MTS monitor, for instance. Other program modules[ may also be intolerant of interrupts. They must be protected by a DI instructions, and at some point must also include EI.INPUT/OUTPUT TECHNIQUES instance an "intelligent" communications
generalized interrupt of interrupts. For terminal might be signal, or by an interrupted by a transmit next character
operator's keystroke. Hardware can be provided to call different interrupt service routines, as we showed earlier. This adds
problem of simultaneous the
If there is not a severe costly to use programmed
priority interrupts. We usually
8.5.3 Vectored Interrupt Systems
This is a combination of hardware and software such that each different source of interrupt calls a service routine specific to the device that created the interrupt.
The prior discussion of RST instructions showed how vectored interrupts can be created by placing different instructions on the data bus in response to INTA. Other schemes are possible, for instance the program may store the address of a module to process the next interrupt, if a particular sequence is expected.
8.5.4 Priority Interrupt Systems
A priority interrupt system is a combination of hardware and software guaranteeing that an interrupt from one source is given priority over another; the higher priority can interrupt the lower, or, if they arrive simultaneously, will be handled first. This can be extended to many levels if necessary.
Specific hardware devices (LSI chips) this function. In combination with create a priority interrupt system.
are available to perform software the 8255 can also
8.5.5 Timed Interrupt Systems
Systems that need to know the time of day often use a hardware counter,
interrupt
operating on the computer's crystal once every millisecond (or
clock, to generate an any other desirable interval).
address in operations
An interrupt service routine increments memory. The service routine may also at this time, checking each input port
a "clock"
conduct 1/0 to see if any service is needed. This scheme provides frequent service to all I/0 ports without requiring each I/0 device to create
interrupts, and is called "polling".
INPUT/OUTPUT TECHNIQUES 8.6 USING INTERRUPTS WITH THE MTS
The MTS provides for vectored interrupts using any of the RST instructions except RSTO, which is the same as RESET The data bus is pulled high by resistors, so that if no external device places an instruction on the data bus, the 8080 will receive FF during interrupt acknowledge. This is the RST7 instruction, which normally enters the monitor program for a STEP or a breakpoint test. You can connect an external device to enter a different RST instruction, using any of the schemes described earlier.
8.6.1 Interrupt Dispatch
The RST instructions enter the monitor program at these locations:
RSTl RST2 RST3 RST4 RST5 RST6 RST7
0008 0010 0018 0020 0028 0030 0038
Since all of these locations are in Read Only Memory you cannot enter interrupt service routines here. The monitor provides for your interrupt service by loading an address from RAM and jumping to that
The actual instruction sequence at the RST location (for RST7) is:
0038 0039
E5 2A 003A EB 003B 83 003C
003D
E3 C9
PUSH H LHLD 83E8
XTHL RET
The RST instruction pushes the program counter into the stack. PUSH H places (HL) into the stack. Now the jump address is loaded into (HL), using LHLD, i.e. the content of location 83E8 is loaded into Register L and the content of location 83E9 into Register H. XTHL exchanges the content of (HL) with the top two bytes of the stack, so the original value of (HL) is restored and the stack now contains the .jump address followed by the address of the interrupted instruction.
RET pops the jump address into the program counter, so the program continues at the address that was stored at 83E8 and 83E9. The same instructions, except for different addresses in the LHLD instruction, exist for each of the seven RST instructions. Your program can store a jump address in the appropriate RAM location, and the RET instruction will then jump to that address. Note that it arrives there with the stack top containing the address of the interrupted instruction, and the registers unchanged, exactly as though the RST
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location had contained a JMP. (RST 4 also contains DI because it is used for programmed calls to the monitor, which must not be
interrupted.)
INPUT/OUTPUT TECHNIQUES
At RESET the monitor loads all the jump addresses. In general your program must replace one or more of these to use interrupts. RST5 and RST6, however, are preloaded to jump into your program area.
Refer to Appendix A, Section A.4.2, for the storage location and preset values.
In the following exercise we will develop an interrupt service routine which will be called instead of the monitor when the RST7 interrupt occurs. This can be exercised by operating in breakpoint mode, so that the MTS interrupt circuit will invoke your service routine after each instruction in your main program. We will demonstrate enabling and disabling the monitor interrupt system.
MAIN PROGRAM
Clear Counter Store jump address for Interrupt Service Test for BRK Key
Not BRK
Enable Monitor Interrupts
Test for CLR Key
Not CLR
Disable Monitor Interrupts
Display High Digit of Count
Interrupt Service Exercise - Main
Figure 8-30
INPUT/OUTPUT TECHNIQUES 8.6.2 Interrupt Service Routine Exercise
The program to be developed uses the monitor interrupt circuit to generate repeated interrupts, much like a timed interrupt system.
The interrupt will call a service routine to increment a two-byte counter in memory. The main program will display the high digit of the count, and test the keyboard. In response to the BRK key it will enable the monitor interrupt system, and in response to CLR, it will disable the monitor interrupts.
When the monitor interrupt circuit is enabled, each instruction in your program will be interrupted, and your interrupt service routine will be called. The dispatch program in the monitor plus your interrupt service will take about 100 microseconds, so the fourth digit of the count (the high digit of the second byte) will count at about 0.4 second intervals.
The solution given used the following memory assignments:
8200 - 820F Initialize
8210 - 823F Main Loop
8248 - 8258 KYIN (Figure 8-9) 8260 - 8270 Interrupt Service
8300 - 8301 Counter
83E8 - 83E9 Store Interrupt Service Address
INTERRUPT SERVICE ROUTINE
Save All Registers
,
(HL)
-
CountIncrement Count Store Count
Restore Registers EI, RET
Interrupt Service Routine Figure 8-31
INPUT/OUTPUT TECHNIQUES 8.6.3 Interrupt Service Routine Test
Figure 8-31 shows the interrupt service routine. This is to be located at 8260, and the two byte counter will occupy addresses 8300, 8301. For a preliminary test of the service routine, use a trivial main program that calls this subroutine repeatedly. This will allow you to step through it and check the stack usage. Write the service routine and test program. (A solution is given in Figure 8-32.) Step through the program. After incrementing and storing the count, examine the stack. It is convenient to load the registers with some easily recognized data so you can identify the stack. The pages following the program solution show a testing procedure and the expected results.
f-UJ
I--LU
INTERRUPT SERVICE ROUTINE
p u s 1-1- /J s r.,J _J~ -./{£'···
Ti> ..Testing Procedure
REG A A 8200 A-OA
NEXT B 8200 B-OB
NEXT C 8200
c-oc
NEXT D 8200 D-OD
NEXT E 8200 E-OE
NEXT 7 8200 F-07
NEXT 8 8200 H-08
NEXT 9 8200 L-09
ADDR, MEM 8200 .CD
STEP 8260 F5
STEP 8261 C5
STEP 8262 D5
STEP 8263 E5
STEP 8264 2A
STEP 8267 23
STEP 8268 22
STEP 826B El
The displays above assume the coding shown in Figure 8-32. Examine the stack after storing the new count.
INPUT/OUTPUT TECHNIQUES Testing Procedure (continued)
ADDR 1/P MEM 83D6 SP.09 Register L
NEXT 83D7 08 Register H
NEXT 83D8 OE Register E
NEXT 83D9 OD Register D
NEXT 83DA OC Register C
NEXT 83DB. OB Register B
NEXT 83DC 07 Register F
NEXT 830D OA Register A
NEXT 83DE 03 Return
NEXT 83DF 82
If you have pushed the registers in some different order, their data will be in a different sequence in the stack.
Check the registers again. Note that only Hand L have been changed, since the interrupt service routine used no others. Change the data in the registers.
etc.
REG A 0
NEXT
0
826B 826B 826B 826B
A-OA A-00 B-OB B-00
Now step to the return instructions.
ADDR, MEM STEP STEP STEP STEP STEP
826B 826C 826D 826E 826F 8270
El Dl Cl Fl FB C9
Check the registers again to be sure that they have been restored properly, and check the stack top to be sure it contains the return address.
ADDR 2/T MEM STEP
8203 ST.C3 8203 C3
Whenever you write an interrupt service routine, it is a good idea to test it this way. Debugging an interrupt service routine in real time operation is difficult because the monitor is disabled when an interrupt has occurred.
8.6.4 Memory Change Breakpoints
Before going on to the main program, we will use this test program to demonstrate the memory change breakpoint system in the monitor.
RESET ADDR 8300 BRK
8200 CD 8300 ??
8300 BP
Since 8300 contains data rather than an instruction, the program counter should never reach this value. Your program will change the
INPUT/OUTPUT TECHNIQUES data stored here, however, and the monitor breakpoint system will stop your program when that occurs.
ADDR RUN
8200 CD 826B El
The SHLD instruction has changed the content of 8300, and your program is stopped after that has happened. Check the breakpoint.
BRK 8300 BP.00
Note that the 00 displayed here is not the content of 8300, but is the breakpoint count. Display the memory content by:
ADDR 8300 MEM 8300 .01