3. CENTRAL HARDWARE
3.2.5. Interrupt Processing Control
The UNIVAC 90/60 System contains an efficient multilevel interrupt system. The processor can react to external and internal error conditions or monitoring conditions by means of this interrupt system. The hardware and associated software allow the processor to change from the user program state to the privileged or supervisor state.
The types of interrupts employed in the UNIVAC 90/60 System are:
• Machine Checks
This interrupt request occurs when a hardware malfunction is detected by the processor or when a hardware malfunction not identified as a subsystem fault is detected by the I/O section, or when a program exception is generated while being masked.
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• Program Exception
This interrupt request occurs when a program error is detected by the hardware. The interrupt is generated as a result of one of the following:
Operation Exception
An illegal processor operation has been attempted or an operation using a nonexistent processor feature has been attempted.
Privileged Operation Exception
A privileged operation has been encountered in a problem mode.
Execute Exception
The object of an execute instruction is another execute instruction.
Protection Exception
The key in key storage does not match the key in the program status word.
Addressing Exception
Reference is made to a nonexistent storage location.
Specification Exception
An integral boundary reference error has been made; general register pairs or floating-point registers have been specified incorrectly; the length of decimal fields is incorrect. The control indicators set by an LBR or BeRE instruction are invalid.
Data Exception
The operands in decimal and editing operations contain incorrect digit and sign codes; decimal arithmetic fields are aligned incorrectly.
Fixed-Point Overflow Exception
The result of a fixed-point arithmetic operation has caused a high-order carry, or a shift operation has
caused the loss of significant bits. '
Fixed-Point Divide Exception
The quotient exceeds the size of the associated register, or the result of a decimal-to-binary conversion operation exceeds 31 bits.
Decimal Overflow Exception
The capacity of the result field is exceeded during a decimal arithmetic operation.
Decimal Divide Exception
The quotient field exceeds the capacity of the quotient part of the result field.
Exponent Overflow Exception
The characteristic result exceeds 127 during a floating-point arithmetic operation.
Exponent Underflow Exception
The characteristic result is less than zero during a floating-point operation.
Significance Exception
A floating-point addition or subtraction results in a zero fraction.
Floating-Point Divide Exception
Floating-point division is attempted with a zero divisor fraction.
Indirect Address Exception
An indirect address control word (lACW) with an incorrect format has been referenced.
Indirect Address Specification Exception
A main storage reference has exceeded the 8-level indirect addressing capability.
• Program Analysis
this interrupt request occurs during program monitoring and certain program tracing operations.
• Supervisor Call
This interrupt request occurs as a result of the execution of a supervisor call (SVC) instruction and may have up to 256 different states which are established by the software.
• External
This interrupt is associated with maintenance trace, interrupt key, and the direct control and external interrupt feature. The direct control and external interrupt feature provides for the direct connection between two UNIVAC 90/6Q Processors. The external interrupt request associated with this feature occurs when certain of the signal-in lines associated with the direct control interface of an object processor are enabled. The states within this level are:
Maintenance Trace Interrupt Key
External Signal 2 State * External Signal 3 State * External Signal 4 State * External Signal 5 State * External Signal 6 State*
External Signal 7 State *
*This state is a part of the direct control and external interrupt feature.
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• Timer
This interrupt request occurs when a present time interval expires.
• Other Input/Output Channels
An interrupt request occurs when status is generated or received from a subsystem during channel or subchannel op~rations. Each channel has its own interrupt to reduce software overhead associated with interrupt analysis.
Selector Channel 1 Selector Channel 2 Selector Channel 3
MUltiplexer Channel Standard Multiplexer Channel DCS
3.2.6.
Instruction RepertoireThe power and flexibility of the UNIVAC 90/60 System are reflected in the instruction repertoire and their execution times. The full repertoire includes all nonprivileged instructions of the IBM System/360 universal instruction set. The instruction repertoire has also been enhanced to facilitate dynamic program relocation and indirect addressing.
3.2.6.1.
Instruction TypesInstructions can be two, four, or six bytes in length. All instructions have an even address. The object formats of the five instruction types are shown in Figure 3-1. The symbols used in Figure 3-1 are explained in Table 3-1.
Instruction
Figure 3-1. Basic Instruction Formats (Object Code Form)
• Register to Register (R R) Instructions
The R R type instructions are used to process data contained in registers. The maximum length of the data that can be handled is a doubleword. The data may be a signed or unsigned binary number, a short or long format floating-point number, or a decimal number, depending on the specified operation. Operand 1 specifies either a register or a mask. Operand 2 specifies a register.
Some R R type instructions use both operands 1 and 2 as an immediate data operand.
• Register and Indexed Storage (RX) Instructions The RX type instructions are used to process data between
• Register to Storage (RS) Instructions
The RS type instructions are used to perform multiple register and storage operations as well as data shifting.
The first and third operands specify the numbers of two general registers or the boundaries for general register usage. Operand 2 specifies a main storage location, which may be further modified by relocation and indirect addressing, or maybe a shift count.
• Storage and Immediate Operand (SI) Instructions
The SI type instructions are used to perform operations on an 8-bit value, called immediate data, and an operand in storage. Operand 2 specifies the immediate data or mask. Operand 1 specifies a 1-byte or halfword storage location which may be further modified by relocation and indirect addressing depending on the operation.
• Storage to Storage (SS) Instructions
The SS type instructions are used to perform operations on two operands located in storage. In logical operations the operands are assumed to be equal in length and may be from 1 to 256 bytes. In decimal operations the operands may be different lengths and may be from 1 to 16 bytes.
SYMBOL
Table 3-1. Svmbols Used to Describe Operand Formats
MEANING
I nstruction operation code
Number of the register addressed as operand 1, a mask, or a register which is the first register of a mu Itiregister group
Number of the register addressed as operand 2
An expression representing a register which is the last register in a multiregister group, an increment, an operand address, or a control storage address.
Number of the register to be used as an index for operand 2 of an RX instruction Immediate data used as operand 2 of an SI instruction
Length of operands 1 and 2 as stated in source code* a reduction of 1 in length when converting source to object code.