Insertable B-Layer

The Insertable B-Layer (IBL)[40]is a fourth pixel layer, which was added to the existing ATLAS Pixel Detector in 2014 (see Figure4.3). It is located at a radius of 33.4 mm between

Figure 4.3:Photograph of the IBL installation into the Inner Detector of the ATLAS Experiment [41].

a new beam pipe with a smaller radius and the current inner pixel layer. The main motivation of the IBL is to provide a robust tracking performance as the instantaneous luminosity of the LHC increases and the radiation damage compromises the performance of the inner pixel layers. The small IBL radius improves the vertex resolution and the b-tagging performance.

At the same time, the location close to the interaction point required more radiation hard sensors and readout electronics, which need to withstand with fluences of up to 5×10¹⁵ n_eq/cm² and 2.5 MGy total ionising dose, respectively. To cope with the high occupancy, the pixel size was reduced to 50×250 µm² and a more efficient readout chip was necessary. The available space between the new beam pipe and the inner pixel layer does not allow module overlaps in the direction along the beam. Thus, geometrical inefficiencies of the modules needed to be reduced. In the radial direction the modules are inclined by 14^◦.

The IBL comprises two module layouts, which use the same readout chip, the Front-End I4B. They are bump-bonded to two sensor technologies that differ in the readout electrode geometry: planar and 3D electrodes. The roughly 2×4 cm² silicon sensors with planar electrodes are connected to two readout chips, forming double-chip modules. These 168 modules are located in the middle of the barrel and represent 75% of the total area. The other 25% of the IBL area are covered with 122 silicon sensors with 3D electrodes, which are connected to only one readout chip, so-called single-chip modules. They are placed at the outer barrel regions. The total area of the IBL is approximately 0.18 m² with a total number of approximately 12·10⁶ pixels.

To optimise the tracking and vertexing performance, the material budget of the IBL was minimised. The thickness of the sensors and the readout chips was reduced and support

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4 . 2 I N S E RTA B L E B - L AY E R

structures of low density carbon foam were used. The radiation length is below 2%X₀ for perpendicular traversing tracks. Evaporative cooling is used to cool the modules to

−15^◦C.

4.2.1 Sensor

As mentioned above, two different sensor technologies are used for the IBL. The so-called planar modules are 200µm thick and have planar n⁺-doped implants in an n-type bulk of diffusion oxygenated float zone silicon. They are similar to the sensors of the Pixel Detector. To reduce geometrical inefficiencies, the outermost pixels are extended to 500µm and a new guard ring structure was introduced[42]. The number of guard rings was reduced to 13 and the innermost eleven rings are placed below the edge pixel implants (see Figure4.4). Consequently, the inactive edges were reduced to less than 450 µm to match the design requirements. Studies showed that the charge collection efficiency is above the required 97% after the IBL fluence, since the voltage limit for IBL was increased to -1000 V[40].

The 3D silicon sensors are 230µm thick and have a p-type bulk material. Pillars are etched orthogonal to the surface into the bulk and filled with doped silicon to form electrodes. This design decouples sensor thickness and charge collection distance and increases the radiation hardness. Figure4.5shows details of the 3D sensor layout from the two manufacturers. The main difference between the layouts is the column depth.

Figure 4.4:Schematic drawing guard ring structure of the IBL planar sensor. The guard rings are located on the opposite side of the pixel implant. They are shifted below the edge pixel [43].

Figure 4.5:Schematic drawing of the IBL 3D pixel sensor designs of two manufactur-ers [43].

4 P I X E L D E T E C T O R T E C H N O L O G I E S

Because of the short distance between the bias and the charge collecting electrode (≈ 75 µm) the depletion voltage after irradiation is below -200 V. The production of 3D design sensors needs non-standard processing, which results in higher costs and a lower yield. The problem of irradiation-induced defects is still present, although the depletion voltage and thus leakage current is significantly reduced.

4.2.2 Readout chip

The readout chip for the IBL is the Front-End I4 (FE-I4), which has a feature size of 130 nm.

This CMOS technology improves the radiation tolerance because of the thin gate oxide transistors. Thus, the FE-I4 fulfils the requirement to withstand 2.5 MGy total ionising dose. The new readout chip has an area of 20.2×18.8 mm², which is five times the area of the FE-I3 (see Figure4.6), and the active area covers 90% of the chip. The pixel array

Figure 4.6:Picture of the FE-I4 and the FE-I3 to compare the sizes [43].

consists of 80×336 pixels with an analogue and a digital circuitry. The analogue part is comparable to the FE-I3. Both readout chips employ a two-stage amplifier, but in contrast to the FE-I3, the second stage of the FE-I4 amplifier is AC coupled to the first stage.

The digital architecture was improved to cope with the high particle rates. Instead of a column drain readout, placing the trigger logic and data storage in the periphery of the chip, the FE-I4 has a four-pixel digital region, which stores the data locally until the trigger decision. The readout speed was increased to up to 160 MHz.

Figure4.7sketches the analogue pixel logic. The amplifier has two stages, a fast preampli-fier and an AC-coupled second amplipreampli-fier. The preamplipreampli-fier integrates the induced charge of the sensor using a feedback capacitor, which is discharged by a constant feedback current. The global feedback current is set by the 8-bit DACPrmpVbpf. For in-pixel adjust-ment of the feedback current the 4-bit DAC, the so-calledFDAC, is used. Subsequently, the discriminator compares the input signal with the adjustable threshold. The threshold can be controlled by the temperature compensated DAC,Vthin_Alt, which is composed

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