MEMORY PROTECTION
PROGRAM STATUS OOUBLEWORO
PSD FIELDS
The memory protection system provides write protection for individual memory pages. When the CPU is in the Mapped mode (either 512 KB or Extended), each 32 KB memory block of logical program address space may be write protected. Write protection for a 32 KB memory block is selected by setting the protect/unprotect bit that is stored, along with the block address, in the MAP register of the CPU.
When the CPU is in the Unmapped mode (either 512 KBor Extended), 512-word memory pages may be write protected. Up to 256 pages (128K words) can be protected at a time. The sixteen 16-bit Page Protect registers are provided in the Unmapped mode.
Write Protection may be overridden by a CPU operating in the Privileged mode.
The Program Status Ooubleword (PSO) provides information relating to the operation that was interrupted or trapped (Old PSO), and the mode and
instruction address that is to be given control during context switching (New PSO). The format of the PSO is shown in Figure 4-4. .
Execution of any Branch or Branch-and-Link instruction replaces the contents of bits 13-30 of the PSO with the effective address specified by the instruction. In addition, if the Branch instruction specifies an Indirect Branch operation, the contents of bits 1-4 of the PSD are replaced by the contents of the corresponding bit positions in the indirect addresss location.
The PSO fields are coded as follows:
1. PRIV (bit 0) indicates the Privileged mode.
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= Nonprivileged 1 = Privileged2. CCs (bits 1-4) indicate the condition codes.
Bit 1 = CC1 Bit 2 = CC2 Bit 3 = CC3 Bit 4 = CC4
3. EXT (bit 5) . indicates Indexing mode.
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= Off1 = On
4. HIST (Bit 6) indicates last instruction was a right halfword (Old PSO only).
5. AEXP (Bit 7) indicates Arithmetic Exception Trap Mask.
P CONDITION E H A P M B
LAST INSTRUCTION EXECUTED WAS NOT A RIGHT HALFWORD LAST INSTRUCTION EXECUTED WAS A RIGHT HALFWORD AR ITHMETIC EXCEPTION TRAP MASK (OFF)
ARITHMETIC EXCEPTION TRAP MASK (ON)
COMPUTER IS IN PSW MODE (DISPLAYED PSD ONLY)*
COMPUTER IS IN PSD MODE (DISPLAYED PSD ON L Y) * UNMAPPED (DISPLAYED PSD ONLY) *
MAPPED (0 ISPLA YEO PSD ON L Y) * ARE NOT USED
ARE LOGICAL WORD ADDRESS
NEXT INSTRUCTION ISA RIGHT HALFWORD BLOCKED (DISPLAYED PSD ONLY) *
INDICATE MAP GRANULARITY, OO=UNMAPPED AND ALL OTHERS =8K MAP GRANULARITY PROVIDE A WORD INDEX INTO THE MASTER PROCESS LIST (MPL) FOR THE BASE PROCESS NOT USED
RETAIN CURRENT MAP CONTENTS INTERRUPT CONTROL FLAGS
OPERATE WITH UNBLOCKED INTERRUPTS OPERATE WITH BLOCKED INTERRUPTS RETAIN CURRENT BLOCKING MODE RETAIN CURRENT BLOCKING MODE
PROVIDE WORD INDEX INTO MASTER PROCESS LIST (MPL) FOR CURRENT PROCESS NOT USED
..
THESE BITS ARE USED FOR DISPLAY ONLY AND ARE NOT PRESENT IN THE PSD STORED IN MEMORY,Figure 4-4. Formats for PSDI and PSD2
CONDITION CODES
7. MAP (Bit 9) indicates Mapped mode
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= Unmapped mode (Displayed PSD only) 1=
Mapped mode (Display PSD only)8. PROGRAM COUNTER (Bits 10-29) indicate the logical program counter (Word Address).
Bits 10-12 are reserved for possible later use. (They must be zero)
Bits 13-29 are the logical address.
9. NR (Bit 30) indicates next instruction is a right halfword.
10. Blocked (Bit 31) indicates Blocked mode (Displayed PSD only).
11. MAP MODE (Bits 32-33) indicate the Granularity as:
00 = Unmapped
01 = Mapped 8K Granularity 10 = Mapped 8K Granularity 11
=
Mapped 8K Granularity12. BPIX (Bits 34-46) provide a word index into the Master Process List (MPL) for the base process. (Bit 46 is ignored.)
13. Bit 47 = Retain current MAP contents. (New PSD only)
14. EXT INT FLAG (Bits 48 and 49) indicate external interrupt state.
Bits 48 49
0 0 0 1 1 0 1 1
=
Operate with Unblocked interrupts (interrupt level active)=
Operate with Blocked interrupts (interrupt level not active)= Retain Current Blocking Mode (New PSD only)
=
Retain Current Blocking Mode (New PSD only)15. CPIX (Bits 50-63) provide a word index into the Master Process List (MPL) for the current process. Bits 62 and 63 are ignored.
A 4-bit Condition Code is stored in the PSD on completion of the execu-tion of most instrucexecu-tions. These condiexecu-tions may be tested to determine the status of the results obtained.
CC1 is set if an Arithmetic Exception occurs CC2 is set if the result is greater than zero CC3 is set if the result is less than zero CC4 is set if the result is equal to zero
The Branch Condition True (BCT) , Branch Condition False (BCF), and the Branch Function True (BFT) instructions allow testing and branching on the Condition Codes.
MAP Map Segments which concantenates to form the appropriate map contents.
When a PSD is being entered into the CPU, the firmware is faced with one Status Doubleword And Change Map (LPSDCM) instruction.
2. The PSD is being loaded as a result of the software instruction
1. Private data which is unique to that process.
2. Statically shared data which is shared between several processes.
This sharing is known at load (map creation) time. Since there exists in reality only a single copy of the data, it is important to software that a single physical copy of its logical/physical map exists, and that all PSDs using this shared data are funnelled through that copy for both software sanity and usage statistics.
3. Data that is shared by means of dynamic invocation. This data (like a Task Service Area (TSA» is logically "ownedll by a part-icul ar process, but needed by a vari ety of other processes whi ch ar.e invoked by the original process in the course of its execution.
Thi s data is generally of the type that it is a Ilper process global" set of data where any number of Operating System (OS) services need a random subset of the information which defies the organi zat i on as a reasonable parameter package, and is 1 i ke ly unalterable directly by the II owningll process. The
as
services which need this data essentially have a partial map in memory coveri ng thei r pri vate code and data, whi ch must be completed by addi ng thi s i nvocat i on page for them to correctly perform thei r functions.It would be possible to accomplish this dynamic completion of the
as
servi ce map by mov; ng into the servi ce map image in memory, but the complexity of maintaining a stack of these invocations and returns (which are totally unsequenced due to the dispatching strategy) is large, and a dynamic link through the PSD relieves both complexity
and overhead in this area. .
The key elements of the PSD which provide firmware with the ability to satisfy these requirements are two 12-bit fields in the second word of the PSD, the CPIX (Current Process Index), and the BPIX (Base Process Index) .
These two fields are both direct word indices into a software-maintained Master Process List (MPL) which is located in physical memory. It is both reasonable and frequent that the BPIX and CPIX fi e 1 ds of a PSD contain the identical number. The MPL is maintained by the most privileged OS code and any destruction will result in immediate disaster.
When the firmware must initialize the map circuit during the loading of a PSD, the following procedure is followed:
1. Using CPIX, locate the MAP Segment Control Descriptor (MSCD) in the MPL. This word is the controlling factor in map initialization.
This word consists of three fields (see Figure 4-5):
a. Borrowed Bit (Bit 0) - Tells the firmware (1) that the first set of map entri es are to be obtai ned from the BPI X MSCD to satisfy the invocation sharing time of creation of this entry, and (2) the numeric value of the BPIX was unknown (and there exists a multiplicity of BPIXs).
ADDRESS
GENERATION
A MAP Segment Descriptor (MSD) is a single word entry which has two fields (see Figure 4-6):
1. Segment Page Count (SPC) - A count of the number of pages (map locations) which this Segment Descriptor covers.
2. Map Image Descriptor List (MIDL) Pointer - The starting physical address of the map cell block which contains the MAP Image Descrip-tors (MID). A MAP Image Descriptor is a single word with one or two halfword page entries (see Figure 4-7).
If the borrowed bit is set when the firmware locates the MSCD, the first segment descriptor is taken from the segment list which is described by the BPIX, and the second and subsequent segment descriptors are taken from the list described by this MSCD. When this indirection has been completed, the only noticeable impact on further processing is that the first map cell to be loaded from this list is "n" rather than "On (if the borrow bit had not been set).
The variable length of pages described by each segment descriptor word are concantenated into the map until the segment count from the MPL is exhausted. The initialization is complete.
Address generation is accompli shed by addi ng the contents of the i n-struct i on to the contents of the index regi ster to form a 1 ogi ca 1 ad-dress. In the Unmapped modes, the 1 ogi ca 1 address is the same as the physical address. In Mapped modes, a portion of the logical address is used to address the MAP, while the remaining portion is used in the physical address. A graphical representation of the address generation process for each of the four modes is presented in Figures 4-8 to 4-11.
SEGMENT I I I
DESCRIPTOR MAP SEGMENT DESCRIPTOR LIST POINTER
1 .c0~N1 • I I I I ' • • 1 . 1 • • I • • • I • 1
i L :OT·~D
8 • 10 11 12 13 " 16 18 17 18 ,. '" 21 22 23 . . 26 20 '" 20 29 30 31~
BORROW BIT .. 0 IGNORE BPIX= 1 SATISFY BPIX MAP SEGMENT CONTROL DESCRIPTOR FIRST.
(IGNORED IF CONTAINED IN MSDC, POINTED TO BY BPIX)
SEG!'I~ENT PAGE COUNT
Figure 4-5. MAP Segment Control Descriptor (riSCO)
I I I
MAP IMAGE DESCRIPTOR LIST POINTER
I
• • • • • 1 • I I I I • • • I • • 1 . . 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BITS 0-7 NUMBER OF MAP PAGES TO BE LOADED
BITS 8-31 MAIN MEMORY LOCATION OF MAP IMAGE DESCRIPTORS (MID'S)
Figure 4-6. MAP Segment Descriptor (MSD)
H II :
NUP~G~ E~R:
I I IH II :
NU~AG~ E~R.Y
I I II
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31=
INSTRUCTION (X)
ADDRESS
I I
INDEX9 10 13 31 13
00000 lOGICAL MAR
00000 REAL MAR
NOTE: THIS METHOD MAY ADD OR SUBTRACT INDEXED ADDRESSES DEPENDING ON THE SIGN OF THE INSTRUCTION.
Figure 4-8. Address Generation (128 KW)
INSTRUCTION (X)