• Up to 1 Mbyte of DPR
• 10 MHz CPU Clock
• Floppy Disk Controller
• RS232 Interface
• Parallell/O
• Real Time Clock
SYS68K/CPU-2
General Description CPU-2
The SYS68K/CPU-2 board can be used as a single board computer, as well as in high performance multi-processor environments.
The CPU-2 board is available with a 68010 CPU (10 MHz), which is software compatible to the stan-dard 68000, and offers additional features, such as virtual memory management and enhanced error exception handling.
The CPU-2 offers either 512 Kbyte or 1 Mbyte of dual ported dynamic memory. The parallel inter-face and timer device 68230 contains 24 bidirectio-nall/O lines and a 24 bit timer. For real time appli-cations the Real Time Clock 58167A with date and time of day is used.
In addition, the Floppy Disk Controller WD 1770 can control up to four different Floppy Drives with a Shugart compatible interface.
BLOCK DIAGRAM OF THE SYS68K/CPU-2
SYS68K/CPU-2
Features ofthe SYS68K/CPU-2
• Processor 68000 (68010 optional) with 10 MHz clock frequency
• Dual Ported Memory with 512 Kbyteand 1 Mbyte versions
• Parallel Interface with 24 bidirectional I/O lines
• 24 bit Timer with 5 bit prescaler
• Real Time Clock with date and time of day
• 8 bit output register with 8 control/indicator LEDs on the front panel
• Floppy Disk Controller for up to 4 Floppy Disk Drives (Shugart compatible interface)
• All I/O interface devices are able to force inter-rupts
FDD CONNECTOR liD CONNECTOR
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REAL FLOPPY PARALLEL
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I. RS2321NTERFACETIME DISK INTERFACE AND REGISTER
CLOCK CONTROLLER TIMER MODULE .~ ';>- 11..!.~
LOCAL CONTROL I INTERRUPT
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LOCAL BUS INTERFACE -~7 I
16K BYTES I'NTERRUPTJ I~us
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Functional Description
The EPROM array and the 1/0 devices communi-cate with the CPU via their 23 bit address bus and 16 bit data bus. The functional areas are briefly de-scribed in the following paragraphs.
68000 CPU
The CPU packed in a Pin Grid Array with 68 pins contains eight 32 bit data registers, seven 32 bit address registers, two 32 bit stack pointers, a 32 bit program counter, and a 16 bit status register.
The processor is able to react on 7 different inter-rupts from the local and from the VMEbus. Proces-sor clock frequency is 10 MHz.
Virtual Processor 68010
The 6801 0 CPU is a virtual machine, software com-patible to the standard 68000. Error exception handling is optimized. On occurrence of an error the program counter and the access address are stored on the stack for easy handling and diagnos-tics. Therefore the system software is able to cor-rect even catastrophic failures, thus preventing system crashes. The processor clock frequency is 10 MHz.
EPROM Area
The SYS68K/CPU-2 contains two 28 pin sockets for JEDEC compatible EPROM's. The base ad-dress of the EPROM area is selectable and easy to change via plug-in jumpers. Maximum EPROM space is 32 Kbyte when using 27128 devices.
RS232 Interface
The board contains a RS232 compatible interface to transfer information to/from other Data Commu-nication Equipment (DCE). The interface chip used is a Multi-Protocol Communications Controller (MPCG) 68561. This device allows the use of all standard byte or bit oriented protocols in synchro-nous, or asynchronous modes.
The following protocols may be selected:
- Binary Synchronus Communications (BSG) IBM ASCII and IBM EBCDIC
- Character Oriented Protocols (COP) BSC, DDCMP, X3.28, X.21, ECMA-16 - Bit Oriented Protocols (BOP)
SDLC, HDLC/ADCCP, X.25
The internal clock for the modem handshake inter-face is software programmable from 50 to 38400 baud.
The MPCC is able to force an interrupt in a fully asynchronous software handling mode. (Three dif-ferent software programmable interrupt vectors are available.)
Dual Ported RAM (DPR)
The on-board CPU communicates with the dyna-mic RAM storage area via a special bus system.
Transfers tolfrom the DRAM area are controlled by special arbitration logic. The base address and the address modifier code of the DPR is jumper select-able to be at any global address in the system envi-ronment.
The DPR storage array is accessible from the VME-bus and also from the on board CPU under the same access address and the same address modi-fier code. A special mode can be selected so that the DPR array works only as local memory (not ac-cessible from the VMEbus).
Storage capacity is 512 Kbyte or 1 Mbyte of DRAM with access times of 340ns on a READ and WRITE with no access from the 2nd bus.
The on-board auto refresh for the DRAM's forces a maximum delay of 290ns and works transparent to other accesses.
Parallel 1/0 (PItT)
The board contains a special I/O interface (PIIT 68230) with 24 bidirectional I/O lines which are ac-cessible via the second 96 pin male connector. A special jumper can enable the 24 bit timer to drive an interrupt to the local bus. Clock frequency of the PI/T is 8 MHz to provide high data throughputs for critical real time applications.
Real Time Clock (RTC)
The on-board RTC includes a calendar indicating month, day of the month, day of the week, hours, minutes, seconds, 1/100 seconds and 1/1000 se-conds.
An interrupt control register enables or disables the interrupt output of the RTC. A special jumper en-ables the interrupt signal to the local interrupt bus.
The RTC can be connected to the +5V standby power line of the VMEbus or to a special line of the 1/0 connector. Therefore all the data patterns are stored during power failures or in power down mode.
Control Register (CR)
The board contains an 8 bit buffered latch which is used to define the Floppy Disk Drive to be enabled and serves as a general purpose output port.
The levels of the output lines are indicated by 8 LED's on the front panel. These LED's may be used as status and test indicators.
Floppy Disk Controller I Formatter (FDC) The on-board FDC with its fully buffered output (48mA sink) contains an SA450 compatible inter-face for direct connection to Floppy Disk Drives.
With the specially buffered output the drive (1-4)
For asynchronous handling, the FDC can force an interrupt to the local bus.
The interface lines are accessible via the I/O con-nector (flat cable 1: 1 to the Floppy Drive Edge Connector).
Control Logic
On the board there are three switches for control.
The RESET button resets the CPU and all I/O de-vices. Pushing the ABORT button generates an interrupt on level 7. The RUN/HALT switch sets the CPU into HALT mode and is indicated with a red LED, otherwise the green RUN LED is lit when the CPU is in RUN mode.
For easy indication that the board is the current VMEbus master, a BUS MASTER LED indicator is provided on the front panel.
To abort invalid address accesses, a time-out
~ounter is provided on the board. It generates a time-out from 81Ls up to 2 ms Gumper selectable}.
VMEbus Interface
The SYS68K1CPU-2 board is completely VMEbus compatible and drives/receives the address modi-fier (AM) signals. A special address modimodi-fier en-coder is used to provide the short supervisor I/O access and the short non privileged I/O access (AM4 active).
The bus control signals Address Strobe (AS), Data Strobe 0,1 (DSO, DS1), and Write (WR) have drive capability of 64 mA in accordance to the VMEbus specification.
Each interrupt signal of the VMEbus can be en-abled or disen-abled on the board so that in a multi-processor environment several interrupt signals may be reserved for each CPU board individually.
The on-board interrupt sources are handled indi-vidually offering transparent handling and self test capabilities.
For multi-master environments the board contains full slave bus arbitration on one of the four select-able daisy chain levels.
The board works completely asynchronous to the VMEbus and the bus master state so that on-board transfers to/from the I/O from the EPROM area and to/from the Dual Ported RAM can be initiated if an-other VMEbus board is the current bus master.
To provide full address decoding, all addresses which are not on-board (DPR, EPROM, I/O) are de-coded as off-board addresses. This allows confi-guration of contiguous memory space of RAM on a selected address range by means of an additional RAM board.
Features of the resident DEBUGGER package:
• EPROM resident system monitor/debugger
• More than 30 commands for debug, up/down-line load
• One-line assembler/disassembler for assembly language program development
SYS68K/CPU-2
• Full speed execution of system and user pro-grams operating in the VMEbus oriented mono-board microcomputer system
• Terminal capability for up/downline load from another development system or any host com-puter
• Powerful software and system debug com-mand set allowing access to all VME modules plus the full 16 Mbyte direct address range of the VME system bus
• Includes all required installation and operation docu mentation
• Access to monitor resources via vectorized en-tries and the TRAP 14 calling sequence
• Start of a user application program or optional software by command
The CPU-2 DEBUGGER is an EPROM based re-sident package ready for immediate use with the VME monoboard CPU-2.
It provides a powerful evaluation and system de-bugging tool for VME based CPU systems. The EPROM resident package operates in 32 Kbyte of ROM space. CPU-2 DEBUGGER uses the first 1024 words of RAM storage for interrupt vectors and temporary storage. The EPROM resident package is delivered in two EPROM's.
The package permits full speed execution of sys-tem and user developed programs operated in a VME based CPU system environment under com-plete operator control.
Access to monitor resources and configuration control is given by vectorized system entries and a TRAP 14 calling sequence. The DEBUGGER may be utilized with the VME based CPU mono board microcomputer SYS68K1CPU-2 in a standalone environment with only a user provided standard asynchronous ASCII terminal.