The CL480's host interface, shown in Figure 4-1, is intended to provide a simple interface to an eight-bit microcontroller. The host interface provides three distinct functions:
o Coded data input (coded data may be sent through the host inter-face if the CD interinter-face is not used for this purpose)
o Local DRAMIROM access o Internal register access
CL480
Host
CFlEVEL
Figure 4-1 CL480 Host Interface
4.1
Functional Overview
4-1
Host Interface Registers
The host communication functions also include device initialization and microcode loading (if the ROM is not used). Host accesses to the CL480 can be asynchronous to GCK.
4.2 As shown in Figure 4-1, the host processor accesses CL480 resources Host Interface by writing to address registers and reading or writing to data registers.
Registers A combination of five host interface registers are used:
- - - - 0 Three 8-bit address registers: A_MSB, A_MB, A_LSB o Two 8-bit data registers: D_LSB and D_MSB
4.2.1 Host Interface Address Registers
The CL480's address registers allow the host to access the CL480's C-FIFO, local DRAM array or internal GBUS registers by setting A_MSB [7 :6], as shown in Table 4-1.
Table 4-1 Register Address Bits Used to Access DRAMJROM, C-FIFO, and GBUS
A_MSB[7:6] Data From/To
00 C-FIFO
01 DRAM/ROM (No autoincrementl
10 GBUS
11 DRAM/ROM (Autoincrementl
Thus the address register specifies which of four types of operations the CL480 can perform:
o Write to Code FIFO
o Read/write to GBUS (internal registers) o Read/write to DRAM (external memory)
o Read/write to DRAM (external memory) with auto-increment ad-dressing
4.2.2 Host Interface Data Registers
The two host 8-bit data registers, D_LSB and D_MSB, are buffers be-tween the host bus and internal modules.
4-2 C-Cube Microsystems
Transfers from the data registers to the destination specified by the ad-dress registers are triggered on the write operation to D _MSB and the read operation from D_MSB. Therefore, the write and read sequences are as follows:
o Write:
o Set address registers o Write D_LSB register o Write D_MSB register DRead:
o Set address registers DRead D _MSB register DRead D_LSB register
Note: For back-to-back transactions to the C-FIFO, DRAM and internal registers, only the address bytes that differ from earlier transaction( s) need to be re-written a second time.
4.2.3 Accessing Host Interface Registers
The host accesses each of the five host interface registers by issuing a bus access with HSEL[2:0] set appropriately, as shown in Table 4-2.
Table 4-2 Summary of Host Interface Local Registers HSEU2:0]' Register Name Contents
001 A_LSB Address, byte 0 (LSB)
010 A_MB Address, byte 1
011 A_MSB Address, byte 2(MSB)
100 D_LSB Data, byte 0 (LSB)
101 D_MSB Data, byte 1 (MSB)
1. Note: 000, 110 and 111 are illegal combinations which should not be used.
4.2.4 DRAMIROM Access
Bit 4 of A_LSB determines whether DRAM (set to 0) versus ROM (set to 1) is selected.
Host Interface Registers
Host Interface Functional Description 4-3
Host Interface Registers
DRAM Access
When bit 6 of A_MSB is set to 1, the host sets A_MSB, A_MB, and A_LSB to form a 21-bit memory address as shown in Figure 4-2.
14
ROM Address ~r-
DRAM Address---J
DRAM171615 8 7 1 0
L...-_ _ _ _ _ _ _ _ • Auto-increment: 1 = enabled, 0 = disabled
Figure 4-2 DRAM/ROM Address Formed by Host Address Registers This 21-bit memory address is a 16-bit word address, not a byte address.
The address map is shown in Table 4-3.
Table 4-3 Memory Address Map
A_MSB[4] A_MSB[3] A_MSB[2] Memory Accessed
1 ROM Bank 1
1 0 ROM Bank 1
0 1 ROM Bank 0
0 0 ROM Bank 0
0 1 unused
0 0 unused
0 0 1 DRAM Bank 1
0 0 0 DRAM Bank 0
4-4 C-Cube Microsystems
For DRAM accesses, bit 7 of Host address register A_MSB controls au-toincrementing. When autoincrementing is enabled (bit 7
=
1), each 16-bit data transfer between the host and the CL480 causes the DRAM ad-dress to be incremented to the next word.ROM Access
For access of ROM bank 0 versus 1, see Table 4-3.
4.2.5 Code FIFO Access
Host bus coded data may be sent to the CL480 in one of two basic modes:
o Serial mode (through the CD interface), as shown in Figure 4-3 and described further in Chapter 8.
o Parallel mode (through the host interface), as shown in Figure 4-4 and described in this section.
CL480
Figure 4-3 Sending Coded Data on CD Interface
CL480
Host Bus Host
Figure 4-4 Sending Coded Data on Host Interface
Host Interface Registers
Host Interface Functional Description 4-5
Host Interface Registers
In code FIFO accesses through the Host interface, the Host specifies A_MSB[7:6]=00 as shown in Figure 4-6. Then the words written to D_MSB and D_LSB will transfer to the Code FIFO.
15 Coded Data FIFO
0
7 6 5
1
\ l I
0
I
1 I
10101 X
D_MSB D_LSB
Figure 4-5 C-FIFO Register Address Formed by A_MSB
The CL480 can sustain a coded data input transfer rate of up to 2.5 Mbytes per second through the D _MSB and D _LSB registers. The C-FIFO holds 31 words, each of which is 16-bits wide.
4.2.6 Internal Register Access
If the Host specifies A_MSB [7 :6]= 1 0, then the access is an internal reg-ister access, as shown in Figure 4-6.
15 Selected Register o
\ J
'---_---'I 1'---_---'
A_MSB D_MSB D_LSB
Figure 4-6 Internal Register Address Formed by A_MSB
Internal registers that are accessible by the host are listed in Table 4-3.
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Host Interface Registers
Note: Registers are defaulted to the correct value through microcode initialization unless otherwise noted in the Con-figuration Area description given in Section 12.3.
Table 4-4 Internal Registers Decoded by A_MSB
Access A_MSB[5:0] Register Name R/W Description
Ox33 CPU_cntl Rm Selects type of data sent to the CL480
Ox3A CPU_pc Rm CPU program counter
Ox36 CPUjaddr Rm IMEM write address
Ox32 CPUjmem Rm Data for instruction memory (lMEM) OxOF HOSTjnt Rm Host nterrupt register
Ox07 HOST_pia Rm Direction and data for programmable liDs Direct Ox20 DRAMjaddr Rm Indirect address for DRAM controller
Ox21 DRAM_data W Data for DRAM controller registers Ox12 CD_cntl Rm Selects type of data sent to the CL480 Oxl0 CD_cnfg Rm Selects data format for CD interface OxlB AUD_mode Rm Data port to udio mode register Ox03 VIDjaddr Rm Indirect address for video register access Ox04 VID_data W Data for video registers
OxOB VID_csync Rm Composite sync control
1. Indirect register addresses are written to either DRAMjaddr or VlOjaddr.
Host Interface Functional Description 4-7
CL480 Read/write Operations
CL480 read and write operations using the host interface registers are 4.3 described in the next two sections.
CL480 Read/write
os (in)
RtW(in)
HSEL[2:0]
HO[7:0] (in)
OACK(ou~
Figure 4-7
Operations 4.3.1 HostWrite
Figure 4-7 shows typical waveforms for a host write to a host interface register. (See Section 9.2.4 for detailed timing parameters for this oper-ation.) The sequence of events is:
Host Interface Local Register, Write Operation
1. The host drives RIW low to indicate a write operation. It also drives the host register address onto HSEL[2:0] and the write data onto HD[7:0].
2. When the HD[7:0], RIW and HSEL[2:0] lines have settled, the host processor asserts DS.
3. In response to the assertion of DS, the CL480 begins the write sequence and sometime later generates a DACK signal.
4. The CL480 latches the data when DACK goes low.
5. In response to the assertion of DACK, the host deasserts DS.
6. The CL480 responds by releasing DACK. This completes the write cycle.
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CL480 Read/write Operations
4.3.2 Host Read
Figure 4-7 shows typical waveforms for a host read from a host inter-face register. (See Section 4.4 for detailed timing parameters for this op-eration.) The sequence of events is:
CD CD
os lin)
---~\~---~/~---RiW(in)
SEL[2:0]
HO[7:0] (in)
OACK(out)
Figure 4-8 Host Interface Local Register, Read Operation
1. The host drives RIW high to indicate a read operation and drives the host register address onto HSEL[2:0].
2. When the RIW and HSEL[2:0] lines have settled, the host pro-cessor asserts DS to indicate to the CL480 that a host bus read access is in progress.
3. In response to the assertion of DS, the CL480 holds DACK deasserted (high) until it can respond to the read request. Be-cause the CL480 is performing arbitration of its internal data buses during register access, DACK assertion is delayed at least one GCK cycle.
4. When the data is available, the CL480 asserts DACK and drives the data.
5. The host deasserts DS when the data has been read.
6. In response to the deassertion of DS, the CL480 releases DACK and D[7:0].
Host Interface Functional Description 4-9
CL480 Read/write Operations
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