6.2 Floating Point Instructions
6.2.2 Floating Point Load and Store Formats
(big-endian) 63
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(little-endian)
Floating point load and store instructions must use even registers. Table 6-2 shows floating point operands. Table 6-3 shows the floating point load and store formats.
destination the destination register address offset (base)
source the source register
Table 6-2. Floating Point Load and Store Operands
Description Op-code Operand Load Fp
Double l.d destination, address
Single l.s
Store Fp
Double s.d source, address
Single S.S
Table 6-3. Floating Point Load and Store Formats
6.2.3
Floating Point Load and Store DescriptionsTable 6-4 groups the instructions by function. Please consult Table 6-3 for the op-codes.
6-4 Assembly Language Programmer's Guide IRIS-4D Series
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Load Fp Instructions
Store Fp Instructions
Load eight bytes for double sion and four bytes for single preci-sion from the specified effective address into the destination ter, which must be an even regis-ter. The bytes must be word aligned. NOTE: To ensure com-patibility with future machines, we recommend that you use double word alignment for double preci-sion operands.
Stores eight bytes for double sion and four bytes for single preci-sion from the source floating point register in the destination register, which must be an even register.
NOTE: To ensure compatibility with future machines, we recom-mend that you use double word alignment for double precision op-erands.
Table 6-4. Floating Point Load and Store Descriptors
6.2.4 Floating Point Computational Formats
This part of Chapter 6 describes floating point computational instructions.
Table 6-5 shows floating point computational operands. Table 6-6 shows the formats of floating point computational instructions.
Operand destination source gpr
Meaning
the destination register the source register general purpose register
Table 6-5. Floating Point Computational Operands
Absolute Value Fp
Double abs.d destination, srei
Single abs.s
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Negate Fp I
Double neg.d
Single neg.s
Add Fp
Double add.d destination, srei, src2
Single add.s
Divide Fp
Double div.d
Single div.s
Multiply Fp
Double mul.d
Single mul.s
Subtract Fp
Double sub.d
Single sub.s
Table 6-6. Floating Point Computational Instruction Formats
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6-6 Assembly Language Programmer's Guide IRIS-4D Series
Convert Source to Specified Fp Precision
Double to Single Fp Fixed Point to Single Fp Single to Double Fp Fixed Point to Double Fp Single to Fixed Point Fp Double to Fixed Point Fp Truncate and Round Operations
Truncate to Single Fp Truncate to Double Fp Round to Single Fp Round to Double Fp
cvt.s.d cvt.s.w cvt.d.s cvt.d.w cvt.w.s cvt.w.d
trunc.w.s trunc.w.d round.w.s round.w.d
destination, src1
destination, src, gpr
Table 6-6. Floating Point Computational Instruction Formats (continued)
6.2.5 Floating Point Computational Instruction Descriptions Table 6-7 groups the instructions by function. Please consult Table 6-6 for the op-code names.
Absolute Value Fp Instructions
Add Fp Single Instructions
Compute the absolute value of the contents of src1 and put the speci-fied precision floating point result in the destination register.
Add the contents of src 1 (or the
Convert Source to Another Precision Fp Instructions
Convert the contents of src1 to the specified precision, round accord-ing to the roundaccord-ing mode, and put
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the result in the destination regis- (.-ter.
Truncate and Round Instructions
The trunc instructions truncate the value in the source floating-point register and put the resulting inte-ger in the destination floating-point register, using the third (general-purpose) register to hold a tempo-rary value. (This is a macro-in-struction.) The round instructions work like trunc, but round the floating-point value to an integer instead of truncating it.
Table 6-7. Floating Point Computational Instruction Descriptions
6-8 Assembly Language Programmer's Guide IRIS-4D Series
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Divide Fp Instructions
Multiply Fp Instructions
Negate FP Instructions
Subtract Fp Instructions
Compute the quotient of two val-ues. These instructions treat src1 as the dividend and src2 as the visor. Divide Fp instructions di-vide the contents of src 1 by the contents of src2 and put the result in the destination register. If the divisor is a zero, the machine sig-nals a error if the divide-by-zero exception is enabled.
Multiplies the contents of srcl (or speci-fied precision floating point result in the destination register.
Subtract the contents of src2 from the contents of src1 (or the desti-nation) . These instructions put the result in the destination register.
When the difference of two
Table 6-7. Floating Point Computational Instruction Descriptions (continued)
Table 6-8 summarizes the floating point relational instructions. The first relation is unordered.
Condition Relations Invalid
Mnemonic Operation
Table 6-8. Floating Point Relational Operators
6-10 Assembly Language Programmer's Guide IRIS-4D Series
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F False T True
In Table 6-9 srcl and src2 refer to the source registers.
Description Op-code Operand Compare F
The machine provides other Compare Instructions for IEEE compatibility.
Table 6-9. Floating Point Relational Instruction Formats
6-12 Assembly Language Programmer's Guide IRIS-4D Series
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Compare NGLE
Double c.ngle.d srcl, src2
Single c.ngle.s
Compare SEQ
Double c.seq.d
Single c.seq.s
Compare NGL
Double c.ngl.d
Single c.ngl.s
*Compare LT
Double c.lt.d
Single c.lt.s
Compare NGE
Double c.nge.d
Single c.nge.s
*Compare LE
Double c.le.d
Single c.le.s
Compare NGT
Double c.ngt.d
Single c.ngt.s
• These are the most common Compare instructions.
The machine provides other Compare Instructions for IEEE compatibility.
Table 6-9. Floating Point Relational Instruction Formats (continued)
6.3.2 Floating Point Relational Instruction Descriptions