Background
2.2 Hardware Design Trends
2.2.2 Feature Trends
The trending analysis of the hardware parameters of the surveyed platforms shows that, over the last decade, there has been a relatively slow growth in the capabilities of the nodes. Instead, most of the Moor’s Law gains were translated into reduction of the size, cost and power-consumption parameters.
In the remainder of the section, we illustrate these trends by analyzing the evolu-tion of the available resources on the surveyed platforms, focusing on the processing element and the transceiver, as core elements of the node hardware architecture.
To extract the short-term trending information from the collected data set, we aug-mented the raw time/parameter scatter-plots with Locally Weighted Scatterplot Smoothing (LOESS) curves [34] including their 95 ˙% confidence interval regions. For visualization of the long-term trending we used simple linear model fitting.
Processing Element
Figure2.7shows a breakdown of the number of surveyed platform releases each year depending on the “bitness” of theCPU. The bit-width of the architecture can be taken as indicator for complexity of the processing element, and by that it can shed some insight into the computational needs of the target application.
In the collected platform sample, the majority of platforms were equipped with 8-bit and 16-bitCPUs, confirming the relatively moderate data-processing demands in manyWSNapplication domains. The data shows increased use of 16-bitCPUs(mainly represented by the Texas Instruments MSP430MCU) in the second part of the decade.
Year
Number of platforms
0 2 4 6 8 10
0 2 4 6 8 10
0 2 4 6 8 10
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
8−bit CPU16−bit CPU32−bit CPU
Figure 2.7: Breakdown of platform releases per year depending on the bit-width of theCPU.
Although in minority, platforms leveraging more capable 32-bitCPUshave been produced throughout the surveyed time window, indicating the need for higher computational power in some specific high-endWSNapplication scenarios.
In addition to the bit-width, for each of the surveyed platforms, we also collected information about the maximal clock rate, minimal core voltage, as well as the amount of available program and data memory. An initial analysis of the data set has indicated strong clustering of these parameters based on the bit-width of the architecture, making a joint trending analysis over all platforms misleading, as the data exhibits more than an order of magnitude variability across the different bitness groups. To highlight this internal structure, in the following analysis we have resorted to faceting based on the bitness.
Figure2.8shows the results for the trending analysis of the maximal clock rate.
For the surveyed platforms having an 8-bit or 16-bit processing elements, we can see a slow trend toward higher clock rates, but the processing power on these platforms remains relatively constrained and does not exceed low tens of MHz. For the 32-bit platforms, the trend seems to even go towards lowerCPUfrequencies, but the small number of such platforms in the sample prevents making strong conclusions.
Figure2.9shows the trending in the minimum allowable supply voltage of the processing core. In addition to the clock rate, the supply voltage of the core is the main determinant of the power efficiency of the processing element. The results show clear improvement over the last decade for the 8-bit platforms, bringing the minimum supply voltages for theCPUdown in the sub 2 V region, on par with the capabilities of their 16-bit and the 32-bit counterparts.
The developments in the available program and data memory are illustrated
Year
Clock rate [MHz]
0 10 20 30 40
5 10 15 20
−100 0 100 200 300 400 500
●
●
●
●
●
●
●
●
● ●
●● ●
●
●
●
● ●
●
●
●
● ●
●
●
● ●
●
●
●
●
●
●
●
● ●
●
●
● ●
● ●●
●
●
● ●●
●
●
●
●
●
●
● ●
●
● ●
●●● ● ● ● ● ●
●
●
● ●● ● ● ●● ●
●
● ●
● ●
●
●
●
●
●
●
●
● ●
● ●
●
●
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
8−bit CPU16−bit CPU32−bit CPU
Figure 2.8: Trends in the maximal clock rate of theCPUs, grouped by the bit-width of the architecture.
Year
Supply Voltage [V]
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
●
●
●
●
●
●
● ●
● ● ● ● ●
●
●
●
● ●
●
●
●
● ●
●
●
● ●
●
●
●
●
●
● ●
●
●
●
●
●
●
●
●
●
● ● ●● ●
●
●
●
●
●
●
●● ●● ● ● ●
●
● ● ● ●●
● ●
● ●● ●
● ●
●
●
●
●
●
● ●
●
●
●
● ● ● ●
● ●
●
●
●
●
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
8−bit CPU16−bit CPU32−bit CPU
Figure 2.9: Trends in the core voltage of the processing elements, grouped by the bit-width of the architecture.
Year
Program memory [KB]
−50 0 50 100 150 200 250
0 100 200 300
−10000 0 10000 20000 30000
●
●
● ●
●
●
●
●
● ●
● ●
● ●
●●
● ● ● ●
●
●
●
●
●
●
●
●
●
●
●
●
● ●
●
●
●
● ●
●
●
●
● ●
●
● ●
●
●
●
●
●
●
●
● ●
●
●
●
● ●● ● ● ● ● ●
● ●
● ●
●
● ● ●
●
●
●
● ●
●
●
●
●
●
●
●
●
●
● ●
● ●
●
●
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
8−bit CPU16−bit CPU32−bit CPU
Figure 2.10: Trends in the available program memory of the processing elements, grouped by the bit-width of the architecture.
on Figure 2.10and Figure2.11, respectively. The trending analysis confirms that memory remains one of the most constrained resources on the 8-bit and 16-bitWSN
platforms, which comprise the majority in our sample. The program memory shows a very weak growth tendency, but still remains significantly constrained with typical values in the range between 50–150 KB. The data memory is even more scarce: over the last decade it managed to grow up only into the range of about 10 KB, exhibiting similar growth rate as the program memory. Even for the 32-bit platforms, which have one to two orders of magnitude larger memory resources, the trend does not show substantial increase over the surveyed period.
Transceiver
Turning our attention to the communication subsystem, Figure2.12shows a break-down of the number of platform releases per year in the sampled set, depending on the communication standard supported by the used transceiver chip.
The distribution shows a strong interest in non-standard compliant transceivers, throughout the surveyed period. The rapid rise in popularity of theIEEE802.15.4 standard in the second part of the decade is well reflected in the sample set, and the majority of platform releases after year 2004 are using transceivers supporting this standard. Another wireless standard with substantial use is Bluetooth. Despite loosing ground to the 802.15.4-based solutions, it is still often used as secondary communication technology, on platforms supporting two transceivers. In contrast, the number of platforms usingWLAN and DECTcompliant transceivers is almost negligible in our sample.
Year
Data memory [KB]
0 10 20 30 40 50 60
0 5 10 15 20 25 30
−20000 0 20000 40000 60000
●
●
●
●
●
●● ●
● ●● ●● ●
●
●
● ● ● ●
●
● ●
●●● ●
● ● ● ●
●
●● ● ● ●
● ● ●
● ●
●● ●
●● ●
●
●
●
●
●
● ●
●
●
●●
●
●
●
● ●● ● ●
●
●
● ●
●
●
●
●
●
●
●
●
●
●
●
●
●
● ● ● ● ●
● ● ●● ●
●
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
8−bit CPU16−bit CPU32−bit CPU
Figure 2.11: Trends in the available data memory of the processing elements, grouped by the bit-width of the architecture.
Year
Number of platforms
0 2 4 6 8
0 2 4 6 8
0 2 4 6 8
0 2 4 6 8
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
No standardIEEE 802.15.4BluetoothWLAN, DECT,...
Figure 2.12: Breakdown of platform releases per year depending on the communication standard supported by the transceiver.
Year
Carrier frequency [MHz]
500 1000 1500 2000 2500
●
●
●
●
●
● ●● ● ● ● ● ● ●
● ● ● ●● ● ● ●
●
●
●
● ● ●
● ● ●
● ● ● ●
● ●● ● ●
●
●
●
●
●
●
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
Standard
● No standard IEEE 802.15.4 Bluetooth DECT IrDA WLAN
Figure 2.13: Trends in the maximal carrier frequency band supported by the transceiver.
To evaluate the trends in the capabilities of the transceiver chip, in addition to their standard compliance, we have collected information about the frequency band and the maximal data rate and current draw. The trending analysis was performed following the same procedure as for the processing element, using a combination of aLOESSfitting for the small-scale trends and a linear model for the global-trend. Due to the dependence of the transceiver parameters from the supported communication standard, we highlight the standard compliance for each sample with different symbols in the presented raw scatter-plot. In addition, the points in the plot are slightly horizontally jittered to make the overplotting (from the multiple platform releases in each year) more evident.
Figure2.13depicts the trends in the operational frequency of the transceiver.
For the chips supporting multiple operational bands, we have selected the highest frequency band as representative for the analysis. The results mirror the information in the standards histogram, since the standard constraints the operational frequency.
Almost all non-standard compliant transceivers in the sample operate in the 868 MHz and 915 MHzISMbands. The popularity of theIEEE802.15.4 transceivers is evident in the jump of the small-scale trend line towards the 2.4 GHzISMband, after year 2003.
The overplotting in the jittered data points is a fitting image of the crowdedness that exists in the band from the different coexisting wireless technologies. The resulting interference problems are one of the main reason for a recent resurgence in the interest for the sub 1 GHzISMbands that also offer better indoor propagation characteristics.
Figure2.14summarizes the developments in the maximal supported data rates.
Over the surveyed period, the typical data rate on theWSNplatforms has remained relatively low and has not followed the rapid growth in speeds characteristic for
Year
Data rate [kbps]
500 1000 1500
●
●
●
●
●
● ●● ● ●
● ●
● ●
● ● ●● ● ● ● ●
●
●
●
● ●●
● ● ●
● ● ● ● ● ● ●●● ●
●
● ●
●
●
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
Standard
● No standard IEEE 802.15.4 Bluetooth DECT IrDA WLAN
Figure 2.14: Trends in the maximal data rate supported by the transceiver.
other domains like wireless access and home networking, highlighting the different application focus. In the early years of theWSNtechnology, the majority of the released platforms featured non-standard compliant transceivers with very low data rates. The slow growth trend, introduced by the use of theIEEE802.15.4 compliant transceivers the with their standard 250 kbps rate, has been recently additionally strengthened by platforms using modern, efficient non-standard compliant transceivers which support higher data rates (500–1000 kbps). With the higher speeds, the new chips can facilitate further shortening of the application’s active phases, leading to lower duty cycles and better system lifetimes.
For this, the energy penalty of the increased speed should not undermine the potential gains in the shorter active times. Figure2.15shows the trend in the current draw of the transceiver on the surveyed platforms, while sending at maximalTX
power. The results confirm that the energy consumption of the chips has remained relatively stable, moving in the range of few tens of milliamperes. Furthermore, the increase in complexity and speed brought by the newer radios have been achieved without prohibitive increase in the energy footprints.