-"
I LfJ II LfJI
1/IlfJ 14J
·SOI
I ,
/', I
ILfJI ILfJ I
II
I LfJ I
·SNI
I
'II I
I I~ I ILfJ
f1
lfl LiJI
·SNN
I
·SON
W W I
III W
CSNS
-VEL
-ABSVL
Figure 4-6-20 Velocity Generator Timing Chart
E03P-4590-0103A ... B 4-85
4-86
h) Fine Position Detector
The Fine Position Detector circuit pulls out the linear position, that is, the Fine Position (FNPOS) signal the from the POSN and posa signals controlled by Sal, SNI, SNN, and SaN signals. The FNPOS signal is applied to the Smoother, On Track Detector, and Clamp Position De-tector circuits.
i) Smoother Generator
The Smoother Generator circuit polarizes the FNPOS (the polarity of signal which is in accord with the head movement direction) and issues the Smoother (SMTH) signal. The SMTH signal makes the DA signal smooth through the Function Generator circuit (see item (12), below). When the difference between NCAR and PCAR, however, is greater than 96 during Direct Seek mode, or GTZ mode is activated then the SMTH signal is
deactivated.
-j) On Track Detector
The On Track Detector senses the servo head positions on the center of each cylinder within ±4 Ilm and issues an On Track (ONTRK) signal to seek control and fault detect logics.
The timing chart of Fine Position Detect is shown in Figure 4-6-21.
B03P-4590-0103A ... B
II II
*SOI
I "
I
I)
*SNI
JI /I
*SNN
r
*SON }, If
-FNPOS~
FWDD - - - /
SMTH - - - I
ONT~K
Figure 4-6-21 Fine Position Detect Timing Chart
B03P-4590-01 03A ... B 4-87
4-88
k) DA Converter
The DA Converter DAC circuit generates the target velocity during Direct Seek or GTZ operations. When the Direct Seek operation is performed, the Difference Counter bits 01 to 064 are applied to the DAC at the beginning of the seek operation. Whenever the servo head has passed through each cylinder, the TXPLS signal is issued and it decreases the Difference Counter. When the Difference Counter output is equal to or greater than 96, the 01 to 064 signal is clamped to 96 and the DAC out-put is adjusted to be -6.B V.
When the GTZ operation is performed, GTZ and LSPD signals set a target velocity through the DAC.
When the Offset operation is performed, OFACT and OFRVS signals set the offset voltage to a value equivalent to ±3 Ilm from the center of cylinder. The DAC output, -DA signal, is applied to the Function Gener-ator and Clamp Position circuits.
I) Function Generator
When the Difference Counter output is less than 96, the Function Gener-ator circuit converts the DAC output into a smooth waveform by adding the SMTH signal. The Function Generator issues a Function (FUNC) signal which is the optimum deceleration curve for position time and the deceleration current profile.
When the servo control is changed to deceleration from acceleration, the Function Generator adds tHe integrated ACCL signal to the FUNC signal to avoid an excessive force to the actuator.
m) Velocity Error Detector
The Velocity Error Detector circuit issues the Velocity Error (VER) signal, which is applied to the Power Amplifier, after comparing a target velocity (FUNC) signal and actual velocity (VEL) signal. At the termina-tion of Seek operatermina-tion, the Clamped Positermina-tion (CLPOS) signal is applied to the Velocity Error Detector instead of the FUNC signal; which acti-vates the PSD R signal.
n) Accelerate Detector
The Accelerate Detector output, that is, the Accelerate (ACCL) signal, is set by the leading edge of the DRLM signal and reset when the ABSVL signal is equal to the FUNC signal. The ACCL signal is applied to the
Function Generator circuit.
The timing chart of the Target Velocity Generator, for a Direct Seek operation, is shown in Figure 4-6-22, and the timing chart for a GTZ operation is shown in Figure 4-6-23.
B03P-4590-0 1 03A ... B
,
POSN
POSQ
-VEL
OV ,...-""--- 0 V
-DA
•
SMTH
TXPLS
--~I~I~I~I~I~I ~~h~' ~I ~1~1~1.~1~·I~ __
ACCL
Integrated - . / ACCL
I . ,r--J , I
'---II~ "- ... _
-FUNC
'---'---~~.-OV
FWDD
l'lL...-_ _ _ _
VER
r
....,
JJI,
I
::::J OVFigure 4·6·22 Direct Seek Target Velocity Generator
B03P-4590-0 1 03A ... B 4-89
_--""'\O.8V
-VEL--~r---~~---~---__ oV
-0.3 V
VER ~---oV
Figure 4-6-23 GTZ Target Velocity Generator
4-90 B03P-4590-0103A ... B
p) Clamp Gate
The Clamp Gate circuit issues Minus Clamp Position (MCLMP), Plus Clamp Position (PCLMP) and Equal (EQUAL) signals through the adder circuit, which compares the two least-significant bits (NCAR2 and 1) of the target cylinder (NCAR2 and NCAR1) with PAR2 and PAR1 signals from the
Position Decoder circuit.
q) Clamp Position Detector
B03P-4590-01 03A ... B
The Clamp Position Detector holds the position signal at specified levels when the servo head is positioned within three cylinders of .the target cylinder address specified by the two least-significant bits of NCAR and PAR. This extends the area controlled by the servo circuit.
The PCLMP signal sets the Calmped Position Signal (CLPOS) to +2 V, the MCLMP is set to -2 V, and the EQUAL signal enables the FNPOS signal on the CLPOS signal.
The ClPOS signal is applied to the Velocity Error Detector circuit when the PSDR signal goes true at the termination of Seek operation, and is then applied to Low Pass Filter (LPF) when the servo head settles on the specified cylinder.
The timing chart of Clamp Position is shown in Figure 4-6-24.
4-91
POSN Cya
POSO
---.,
I
NCAR2 I
I I I I I I I I I
NCAR1
~
I I I I I I
I I I~
PAR2
I I
PAR1
I I I I
UNSQ
~
I I I I I I I I I I I I I I I I
-EQUAL~ I I I UI I I I I Ii
'----PCLMP
~
I LJJTl I I I I I I I I I I L----li I
r --MCLMP-FNPOS
----'--+++-I--+++++++.J+++-+-f---7----t~++__\r++++_+_++_t_+_---+2 V
I I
CLPOS
-...I---\-+-+--++--+---~_--.l.-_+_++_-__+___+_-~-Figure 4·6·24 Clamp Position Timing Chart
4-92 B03P·4590-01 03A. _. B
r) Low Pass Filter (LPF)
The servo circuits form a feed-back loop during track following after a Seek operation using the position signal recovered from the servo head.
The LPF circuit attenuates unused high frequencies. The LPF has a resonance frequency at 1.9 KHz.
s) Position Error Detector
The Position Error Detector pulls out the phse-compensated Position Error (PER) signal required for the feed-back loop during track following.
The PE R signal is composed of a VE L (phase-compensating) signal, and an integrated position signal; improves stiffness and following character-istics of lower frequencies.
t) Power Drive Multiplexer
The Power Drive Multiplexer circuit passes through either the VE R signal, by activating DRLM signal during Direct seek or GTZ operation, or the PER signal, by activatiog the LNMD signal during track following se-quence.
u) Power Amplifier Driver
The Power Amplifier Driver circuit drives the last stage of the power amplifier. This circuit controls the base current to the power transistors by comparing the input signal with the feed-back signal from the last-stage transistor current.
v) Power Amplifier
The Power Amplifier circuit is a current amplifier which drives the coil of the Voice Coil Motor (VCM). The circuit is composed of four H-type
The VCM Heat Detect circuit senses an abnormal current flowing through the VCM coil or also DC Motor windings.
The coil current of the DC Motor windings current is integrated and con-verted into the VCM Heat Detect (VCMHT) signal.
(2) Direct Seek Servo Control
During a Direct Seek with servo control, the servo head is driven high speed,
When the servo head is positioned within capture distance from the spcified cylinder, the Servo Control mode is changed to Linear mode. During Linear mode (track following), the feed-back loop is formed to minimize the Position Error Signal.
When an Offset operation is performed, the offset voltage is applied to the Position Error signal through the DAC. The servo head is the offset by
±3 pm.
The Linear mode signal flow is shown in Figure 4-6-27.
B03P-4590-0 1 03A ... B 4-93
.j:>.
VELOCITY ABSOLUTE V=Q
GENERATOR VELOCITY -ABSVL DETECTOR V=Q
r
(BH1) GENERATOR (BH1) I - -- (BH1)CD o
FUNCTION SW VELOCITY
SMTH GENERATOR
--. -
ERRORFigure 4-6-25 Direct Seek Signal Flow (Sheet 2 of 2)