Extensions

5.4. EXTENSIONS 91

Table 5.1: Values ofl^F_f(k)for a transistor withL(F) =9and minimum finger length 2 dependent on the value of the parameterfLenMode.

k L(F)/k l^F_f(k)

int r-up r-down

1 9.00 9 9 9

2 4.50 – 5 4

3 3.00 3 3 3

4 2.25 – 2 2

5 1.80 – 2 2

6 1.50 – 2 –

Finger Lengths

The gate contacts of transistors cannot be arbitrarily long. In addition to the natural restriction induced by the usable fins in a cell, the technology spec-ification provides parametersfLenMin andfLenMax that encode lower and upper bounds for l_f(_F) for every FET. In principle, these values could be set individually for each transistor, but the implementation of BONNCELL

requires the same bound for all n-FETs and the same bound for all p-FETs.

Until now we have only assumed|L^F_f(k)| ≤1 but did not give a specification of that function. BecauseL(_F)is supposed to denote the number of fin/gate intersections, the ideal definition would be L^F_f(k) = {L(F)/k}. However, this might not be an integer, thereby contradicting the discrete nature of the length of a finger. The behavior of BONNCELLin this situation can be con-trolled by the parameterfLenMode, which has the three possible valuesint, r-up, andr-down. If it is set toint, then the exact L(F) = n_f(F)·l_f(F)is enforced, meaning that

L^F_f(k)_:=

({L(F)/k} ifL(F)/kis integral

∅ otherwise.

In the other two cases, the only element of L^F_f(k) is the closest integer to L(F)/k, as long as it is within the interval[_fLenMin,fLenMax]_{. If}L(F)_{/kis an} odd multiple of 0.5, then in one of the modes the value is rounded up (r-up) and in the other mode the value is rounded down (r-down). An example of the parameter’s effect is shown in Table 5.1.

Additional Tracks

The definition of the quality measureQ(_Λ)favors layouts that use the min-imum number of tracks over every strictly larger layout. The total width as the primary optimization target is often a good choice in practice, but

5.4. EXTENSIONS 93 sometimes the restriction to minimum-width layouts produces bad results.

In these cases, providing 1 or 2 additional tracks beyond those that are re-quired leads to layouts that need slightly more space yet much less wiring.

In BONNCELL, the issue can be addressed by the integer parameter max-AddlTracks (default: 0). It modifies the quality measure such that all lay-outsΛwithW_opt(F)≤W(_Λ)≤ W_opt(_Λ) +maxAddlTracksare treated as if their width wasW_opt(F), i.e. only the secondary entries of Q(_Λ)influence how different layouts compare to each other. Only when the width exceeds W_opt(_Λ) +maxAddlTracks, layouts are considered strictly worse than all lay-outs that are “small enough”.

The algorithms can easily be adapted to this rule. For example, the loop in line 10 of Algorithm 7 does not stop as soon as a solution has been found, but it continues formaxAddlTracksiterations after that point. Moreover, lower bounds are not compared to the best known solution, but to a number which is the given number of tracks larger than that.

Boundary Condition

When several cells are placed next to each other within a circuit row, it is im-portant that all design rules are satisfied near the gap between them. Because those rules are affected by shapes in different cells, they cannot be captured directly by the layout within a single cell. One way to solve the problem would be to always introduce k unused tracks between neighboring cells, where kis chosen pessimistic enough so that the free tracks suffice to make rule violations in such gaps impossible.

But this strategy would waste much space and a more precise technique is

supported in BONNCELL. For every technology, a set ofboundary conditions boundary condition

is defined that impose additional constraints near the left and right border of a cell. They are designed such that neighboring cells, both of which sat-isfy these constraints, do not violate any design rules. Examples for com-mon boundary conditions are the requirement that source/drain contacts on the leftmost and rightmost track must be connected to the nearby power potential, or that fingers on the leftmost and rightmost tracks must not be longer than some technology-dependent value. The boundary condition can be switched on and off by the user parameterboundaryCondition.

The feature is implemented mainly by causing backtracking as soon as a vi-olation is detected. But it is equally important to adjust the definition of the layout width W(_Λ), which, until now, was determined merely by the gate locations of laid out transistors. The intention of this definition is to denote the width of the smallest cell outline that can contain a given layout. With the addition of a boundary condition we thus need to augment the definition by adding a sufficiently large amount of tracks such that in a cell of widthW(_Λ) the boundary condition near its right border is satisfied (the left border is already covered by the enhanced bounding).

As the extended definition of layout width does not decrease the value of W(_Λ), the lower bounds computed by the algorithms above are still lower bounds. Depending on the technology and its concrete boundary conditions, LowerBoundcan be improved to anticipate the increased value of W(_Λ) in specific situations.

Fixations

In particular cases, a user might want to prescribe a given property that should not be changed by the tool. Several options are provided for that.

A trivial option is to fix the number of fingers for a given FET. In this case L^F_f(k)is simply set to∅for all other finger numbers.

A more sophisticated possibility is to setboundary fixations. For every FET

boundary

fixation it is possible to enforce its placement adjacent to the left respective right cell border, with a source or the drain contact facing outwards. With such a con-straint, it is important to see that layouts now cease to have the property that motivated the definition of canonical layouts: It is not possible anymore to arbitrarily swap and exchange FET groups which are separated by a gap of sized^max. We thus have to modify the definition of canonical placements to exclude the outermost FET groups if they contain a FET that has a boundary fixation and adjust the specialized bounding procedure.

Aside from this, the boundary fixations are implemented in terms of addi-tional bounding as soon as violations are detected.

Flexible Power Strips and Odd Rows

To simplify the presentation, we have always assumed that the bottom bor-der of a single-row cell is covered by a GND power strip and the top borbor-der by aVDD power strip. This is not necessarily the case and BONNCELL pro-vides facilities to change this default power structure.

First, it is possible to define an arbitrary number of power strips with arbi-trary y-coordinates. It is only required that they are disjoint. Power strips can be configured to only have metal on M2 or to be accessible from both M1 and M2. In cells with more than one circuit row, every second row has the same power structure as the bottommost row and all other have a structure which is flipped on the x-axis.

The definition of the power strips, however, does not affect the default be-havior that n-FETs (on multi-row cells: in the bottommost row) are placed near the bottom cell border and p-FETs near the top border (on multi-row cells: the top border of the bottommost row). This scheme can be changed by setting the parameteroddRow. In this case, the cell layout is flipped ver-tically in every circuit row, i.e. n-FETs are assigned to the top and p-FETs to the bottom FET row. Figure 5.9 illustrates the difference.