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(0) CORE VOLTAGE DURING RESETTING HALF CYCLE

o

(b)CORE VOLTAGE DURING FIRING OR "READ-OUT" HALF CYCLE Fig. 6--Pulse-width operations.

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BUFFER STAGE NETWORK ^__

-*~L~OGARIT"MIC ~

UNIT Fig. 7-Details of the logarithmic circuit.

unit in this circuit and the basic circuit shown in Fig. 1 is the inclusion of a second transistor switch T2 of the germanium p-n-p type for the purpose of minimizing the effect of leakage current through the main transistor switch T1. Since this second switch T2 is closed when-ever the main switch Tl is opened and since T2 is con-nected in the inverted connection,S its extremely low voltage drop effectively shunts the leakage current of T1.

The exponential pulses required for the logarithmic operation are obtained from a dc source by means of a magnetic-coupled transistor square-wave generator,4 a transistor buffer stage and a RC differentiating network as shown in Fig. 7. The diodes connected to the bases of Tl and T2 maintain the input impedance seen by the exponential function generator essentially constant over a full cycle. The diodes also serve the purpose of reduc-ing the Zener voltage requirement of Tl and T2.

The input voltage Ei is so connected that it modulates the zero level of the base current of Tl during the half cycle in which the capacitor C L discharges. An analysis of the circuit transient shows that the time constant

as-3 R. L. Bright, "Junction transistors used as switches," AlfiE Trans., vol. 74, p. 111; March, 1955. '

4 G. H. Royer, "A switching transistor d-c to a-c converter having an output frequency proportional to the d-c input voltage," AlEE Trans., vol. 74, p. 322; July, 1955.

Schiewe and Chen: A nalog Logarithmic and A ntilogarithmic Circuits 125 sociated with this discharge, which becomes the T L in

(1)-(3) of previous discussion, is given by

TL = CL[R1

+

R2Ra/(R2

+

Ra)

J.

⁽¹³⁾

The base current of the transistor Tl has the waveform shown in Fig. 8, in which the portions a and b are deter-mined by the relation

b RIR2

+

^R2Ra

+

^{RaRl Ei}

- - - - =

---a

+

b R2(R2

+

Ra) EL' (14) Thus, the maximum value for Ei , or the upper limit of the input to the logarithmic circuit, can be determined by setting a = 0 and becomes

R2(R2

+

^Ra)

Ei max = E'L.

RIR2

+

^R2Ra

+

RaRl

(15) The lower limit of the input Ei min is dictated by the minimum base-to-emitter voltage required for the sili-con transistor Tl to perform as a closed switch. The choice of the supply voltage levels and the RC com-ponent values as given in Fig. 7 was based on the con-sideration of the Zener voltage and current gain capa-bilities of the available transistors, and the objective of obtaining maximum operating range of the logarith-mic circuit for a supply frequency of 1000 cps.

The steady-state temperature characteristic of the logarithmic circuit is shown in Fig. 9. All transistors and diodes used in the logarithmic circuit under test and in the antilogarithmic circuit to be described are of the following types:

Si diodes --lN137A

Si n-p-n transistors--904 (Texas Instruments, Inc.) Ge p-n-p transistors-2 N 74

Ge n-p-n transistors-4815C.

The only parts of the circuit which were subjected to tern perature changes were the semiconductor com po-nents in the logarithmic unit. Under these conditions the experimental tests indicate the maximum error to be within 1.5 per cent of the full-scale output for the temperature range from O°C to +71°C with a corre-sponding input range of 0.7 to 120 volts.^s The major cause of error is the lack of sharpness at the trailing edge of the output voltage pulse as the transition time of the transistor switch from conducting to cutoff lengthens at low input. The maximum error increased above the value of 1.5 per cent as temperature' decreased from O°C to -60°C. This effect is believed to have been caused by a significant decrease in current gain of the silicon transistor for temperatures in this range.

The stable operation of the logarithmic circuit within the temperature range of O"C to +71°C is attributed to the operation of the transistors in the switching mode.

For the same reason the circuit possesses the important property of reproducibility. The characteristics do not

6 The errors in measurement were estimated to be 1 per cent.

Fig. 8-Base current waveform of the main transistor switch in the logarithmic circuit.

12

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,

1.0 10 100

DC INPUT VOLTAGE (Ej) -VOLTS

Fig. 9-Steady-state temperature characteristic of the logarithmic circuit.

1000

depend upon a particular transistor or upon special matching of components which is experienced in many contemporary circuits. Also, simplicity has been achieved even if the generation of the exponential pulses is taken into consideration. The circuit gains reliability and long life from the use of transistors and magnetic cores as the only active elements.

ANTILOGARITHMIC CIRCUIT

Details of the antilogarithmic circuit are shown in Fig. 10 (next page). Here the input is assumed to be a dc voltage. A sawtooth function generator, which mixes a square wave with a triangular wave in proper pro-portion to produce the desired output waveform, is in-cluded in the circuit for the purpose of converting the dc input Ei to the form of pulse width (~T-WA ). The exponential voltage pulses required as the voltage sup-ply for the output of the antilogarithmic unit are gen-erated by periodically charging and discharging the 0.04 p.f capacitor (lower portion of Fig. 10). The ger-manium p-n-p transistor T2 and the two diodes in the antilogarithmic unit are employed for the same reasons given in the discussion of the logarithmic circuit.

The steady-state characteristic of the antilogarithmic circuit at room temperature is shown in Fig. 11. The maximum error is within 1 per cent of the full-scal~ out-put for an outout-put voltage range from 0 to 1.5 volts.,The

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SQUARE WAVE OSCILLATOR

EXPONENTIAL FUNCTION GENERATOR

ANTI LOGARITHMIC UNIT

Fig. lO-Details of the antilogarithmic circuit.

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Fig. ll-Steady-state characteristic of the antilogarithmic circuit.

10

major source of error is the inherent approximation given by (5) and (6) and the imperfect linearity of the saw-tooth waveform. Comments on the reproducibility, reli-ability, and long life of the logarithmic circuit apply also to the antilogarithmic circuit. Simplicity and temperature stability of the antilogarithmic circuit in Fig. 10 are somewhat poorer because of the employment of the low-voltage sawtooth function generator, which, however, is not needed in the ensemble circuit described below.

LOGARITHMIC-l\1AGNETIC CORE-ANTILOGARITHMIC ENSEMBLE

Details of the ensemble circuit with two inputs are in Fig. 12 (opposite). The two logarithmic units, the pulse-width algebraic unit, and the antilogarithmic unit are the heart of the ensemble. Accessory equipment con-sists of several transistor buffer stages, several expo-nential function generators, a square-wave oscillator which synchronizes the operation of the different parts of the ensemble, and a delay network which keeps the output pulses of the logarithmic units from overlapping.

The logarithmic units differ slightly in physical layout from that in Fig. 7. First, they are operating during the charging periods of the capacitors C1 and C2• This was necessary in order to be able to introduce the delay net-work and to use silicon transistors in the logarithmic units. (Only n-p-n type of silicon transistors was cavail-able at the time of the circuit development.) The in-versely connected germanium transistor in Fig. 7 is not used here because it would interfere with the operation of the pulse-width algebraic unit.

The delay network is composed of a magnetic core and a biased rectifier. The core is so designed that it is saturated upon absorbing one-half the volt-time area per pulse put out by the square-wave oscillator. There-fore the operation of the .upper logarithmic unit lays be-hind the operation of the lower one by a quarter cycle.

SQUARE -WAVE OSCILLATOR

I

I I I ,

I

1

Schiewe and: Chen: Analog' Logarithmic and=A ntilogarithmic Circuits

EXP. M

TRANSISTOR FUNC. LOGARITH.IC

DELAY BUFFER STAGES GENS. UNITS

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1 _ _ _ - _ _

1 _ _ _ _ _ _ 2.-'< _ _

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EXPONENTIAL FUNCTIO N GENERATOR

Fig. 12-Ensemble circuit.

127

The pulse-width algebraic unit operates in accordance with the principle discussed previously. The transistors of the log units close during part of the reset half cycle, and the transistor of the pulse width unit closes during the entire firing half cycle. Since the same voltage Ebb is applied to the core during both reset and firing opera-tions, its variation has no first-order effect on the accu-racy of the pulse-width algebraic performance.

200

/v ^/

In order to operate the antilogarithmic unit, a pulse width corresponding to (~T-WA ) is required where WA

is the width of the winding voltage pulse of the magnetic core during the firing half cycle. This pulse width of (!T- WA ) is easily obtained as the current waveform picked up by the resistor Rc and is then used to drive a transistor amplifier which in 'turn drives the anti-logarithmic unit. All remaining parts of the ensemble circuit have been discussed previously.

The ensemble circuit has been operated as a simple multiplier with two inputs and the resultant character-istic at room temperature is shown in Fig. 13. This was achieved by choosing the circuit parameters so that

7 L=7A, Ebbl=ELb2=E, N1=N2=N, and n=2 in (12).

With the omission of one logarithmic unit and halving the reset voltage (by connecting the emitter of the

re-(f)

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t-50 100 150 200

FIRST INPUT VOLTAGE (Ej) -VOLTS

Fig. 13-Steady-state characteristic of the ensemble operating as a multiplier.

maining log unit transistor to the center tap of Ebb), the same circuit was made to operate as a square-ropter with the resultant characteristic at room temperature shown in Fig. 14. This operation corresponds to T L =T A, Ebbl

=

!E,

Nl

=

N, and n

=

1 in (12). Of course, any other op-eration representable by (12) can be achieved by the highly flexible ensemble circuit in Fig. 12 without any modification of the basic circuit configuration. The re-quirement for each additional input is a logarithmic unit and a delay network. The over-all accuracy of the en-semble characteristics as indicated by Figs. 13 and 14 is in the order of 2 per cent.

CONCLUSION

A logarithmic circuit and an antilogarithmic circuit using switching transistors have been developed based on the principle of modulating exponential voltage pulses. The main feature of these circuits is their quality of reliability and reproducibility not found in contem-pory circuits of the same degree of accuracy. Also, good stability with temperature variations has been achieved by operating the transistors as switches. Time con-stants of the exponential pulses can be made stable by the use of negative-temperature-coefficient resistors and mica capacitors. The circuit performance also ap-proaches the other objectives listed in the introduction of this paper. An ensemble of the logarithmic and anti-logarithmic circuits interconnected through a pulse-width algebraic unit keeps the over-all response time within one cycle of the supply frequency if the output

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10 100 1000

fNPUT VOLTAGE (Ej) -VOLTS

Fig. 14-Steady-state characteristic of the ensemble operating as a square-rooter.

pulse waveform is acceptable. The ensemble has such a high degree of flexibility that it should find applications in many computing systems.

ACKNOWLEDGMENT

The development work which led to this paper was done when both authors were with Westinghouse Elec-tric Corporation. The authors wish to acknowledge the technical guidance rendered them by Dr. G. F. Pittman and R. O. Decker, and the assistance by I. Gerson in the improvement and measurement of the ensemble circuit.

High-Speed Digital-to-Analog Conversion by

Im Dokument JOINT COMPUTER (Seite 125-129)