Drain Current Digitizer (DCD)

The drain current digitizers [57] (DCD) ASICs are located at the end of the matrix and digitise the drain currents of the DEPFETs. During the development phase of the PXD project there have been multiple versions of the DCD. The version used on the half-ladders that are installed in Belle II is called DCD4.2.

Each DCD has the capability to digitise 256 currents in parallel. Of those inputs only 250 are used, resulting in the parallel readout of 1000 pixels in one readout cycle as there are 4 DCDs on each half-ladder. For the digital output to the DHP the DCD has eight 8-bit wide outputs, where each of these outputs is used to transfer the data of 32 channels. To test the communication with the DHP the DCD can be put into

4.5. PXD half-ladder and Front-end readout test pattern mode. In this mode it will output a predefined test pattern which can be checked against to verify a stable communication between DCD and DHP.

Digitization and Parameter Optimization

The analog to digital conversion (ADC) of the drain currents is done using a redundant signed-digit conversion. The comparison of currents that is needed for this method is done via current memory cells. At the end of the conversion an 8-bit digital code is generated, representing values within the range from 0 to 255 ADU (ArbitraryDigital Unit).

The quality of the digitization process can be evaluated by looking at ADC transfer curves. These curves are generated by feeding a known current into the DCD and checking the digitised result. The are multiple current source available to record the transfer curves. The DCD itself has a built-in current source that can be used for this purpose. Yet, measurements have shown that this current source has a non negligible noise and is therefore not the optimal solution. Another possibility is the use of the DEPFETs themselves and their drain currents. By varying the applied gate voltage V_Gate the drain current of the DEPFETs can be steered to record an ADC curve. The disadvantage of this method is the non-linear dependency of the drain current on the gate voltage. The last possibility is an external current source. An example of such a

Figure 4.13.: Two dimensional histogram of a recorded ADC transfer curve. The curve was measured by varying the DEPFET gate voltage VGate to control the input current into the DCD while recording its response O_DCD. While the curve covers the whole output range of the DCD and no code jumps are visible, the linearity of the curve for high values of ODCD is sub-optimal as the linear fit shows.

curve can be seen in fig. 4.13. These curves are used to judge the following criteria:

Linearity, dynamic range (min. output code and max. output code), missing codes and noise. ”Missing codes” refers to cases where certain output codes are not present in the curve, resulting in gaps within the curve. This error can occur when the current memory cells are not configured optimally. Based on these criteria the curves are categorised as grade-A/B/F. In appendixAmore details about the quality criteria and the grading are given together with more examples of ADC transfer curves.

The DCD features several settings to configure the digitization process called DACs.

These DACs have to be optimised together with two reference voltagesV_refinandV_amplow. In total there a five adjustable parameters that have a significant influence on the digiti-zation process of the DCD. For practical reasons the parameter space is sliced to reduce the complexity of the optimization process. Measurements in the laboratory have shown that performing two 2-dimensional and one 1-dimensional scan in the 5-dimensional parameter space reliably produces an setting which fulfils all quality criteria. A com-prehensive and detailed description of the optimisation process for DCD can be found in [61].

Common Mode and Offset Correction

In addition to the pure digitization of the drain currents, the DCD has two additional features built in that improve the overall performance of the system. The first one is the analog common mode correction (ACMC). It uses an analog feedback circuit to remove electronic common mode noise from the drain currents before the digitization is started.

During this correction the DCD calculates the mean of all incoming currents and sub-tracts it from the individual drain currents. Because the DCD digitises one gate after another, the common mode correction is also applied per gate. The ACMC is optional and can be switched off, which is required for certain kinds of calibration measurements.

The second important feature of the DCD is the so-called 2-bit DAC correction. It describes a mode of operation in which the DCD adds a predefined offset current IDAC

to the input currentIin. This offset current can be set for each drainline and conversion cycle individually, allowing a per pixel correction. While the size of the offset current is set globally, the effect on each pixel can be adjusted in four levels:

0 : I =Iin+ 0×I_DAC 1 : I =Iin+ 1×IDAC

2 : I =Iin+ 2×IDAC

3 : I =I_in+ 3×I_DAC

This allows to decrease the width of the input current distribution significantly. The input current distribution is divided into four parts of equal width. The highest setting (3×IDAC) is applied to the lowest part of the four while the second highest is applied to the second lowest part and so on. Figure 4.14 shows a graphical sketch of this procedure. Because the DCD does not have a memory to hold the information for which

4.5. PXD half-ladder and Front-end readout

Figure 4.14.: Idealized representation of the offset correction principle. The pedestal distribution of the sensor (typically Gaussian) is divided into four parts (a). The pixels belonging to the three lowest parts are shifted by adding a current from the DCD. Ideally the resulting distribution has a four times smaller width (b).

pixel which correction has to be applied, this information is stored in the DHP memory.

The DHP sends out a control signal to the DCD during each digitization cycle to steer the correction.