4.3.1~
The Double-Word Memory Reference instructions require two consecutive memory locations and allow direct and indirect addressing. Indexed addressing is not allowed and is. in fact. not useful. since these instructions manipulate both the A arid X registers. The format for Double-Word Memory Reference instructions is shown in figure 4-8.
OP-CODE r]EXPRESSION
I~EXPRESSION
2] [COMMENTS]No Operator = Direct Address
*
:= Indirect Addressing (multi-level)EXPRESSION 1: any absolute or relative expression defining the effective memory location.
EXPRESSION 2: an optional instruction count in the range 0 thru 31 for NRM.
Figure 4-8. D,.·,ble-Word Memory Reference Format
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4.3 . 2 Instructions
DVD DIVIDE. Divides contents of the A and X registers by contents of memory location addressed by Expression 1. This address pointer (Expression 1) may be direct or indirect and occupies second word of double-word DVD instruction.
Prior to execution of instruction. A and X registers contain signed 30 bit dividend· (as shown in figure 4-9). and addressed memorY location contains. signed full-word divisor. Both dividend and divisor must be positive.
Quotient is placed in X register (sign plus 15 bits) and fractional remainder in A register (sign plus 15 bits). OV is set if a divide fault occurs (Divisor ~ most significant half of dividend). If no divide fault occurs. OV is returned to original state (prior to DVD instruction) . Note that least significant half of dividend is 15 bits. left justitied.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 I! 7 6 5 4 3 2 1
1
0I
DIVIDEND (MSHIl I
DIVIDEND (LSH,A REGISTER X REGISTER
I
0 XI
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13. 12 11 10 9 8 7 6 5 4 3 2 1 0
L(S-LI _____________ R_E_M_A_IN_D_E_R ____________
~I 151
QUOTIENTMPY
A REGISTER X REGISTER
Figure 4-9. Divide
MULTIPLY AND ADD. Multiplies contents of X register by contents o.f the memory location addressed by Expression 1 and then adds contents of A register to product. Address pointer <Expression 1) may be direct or indirect and occupies second word of double-word MPY Instruction.
Prior to execution of MPY instruction. X register contains signed word multiplicand. addressed memory location contains full-word mUltiplier. and A register contains " offset If to be added. (Refer to figure 4-10.) Multiplier and offset must be positive or zero ..
Multiplicand may be either positive. negative or zero. Result IS
placed in A and X registers (sign plus 30 bits). Note that least significant half of result is a I5-bit left justified value consistent with format of least significant half of dividend.
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In aU cases OV will be reset (= 0) at completion of a full multiply. The contents of1JV prior to execution of MPY will be returned in the least signiftcant bit (bit 0) of the X register.
15 14 13 12 11 10 9 8 7 .. 5 4 3 2 1 0 15 14 13 12 11 10 I 8 7 .. 5 4 3 2 1 0
l-Jlo II..--______
OFF_SET _ _ _ --"I s I
MULTIPLICANDA REGISTER X REGISTER
15 14 13 12 11 10 9 8 7 " .. 4 3 2 1 0 15 14 13 12 11 10 • 8 7 , 5 4 3 2 1
I ...
S...JI ... _ _ _ _ _ _ RE_S_U_LT_'_MSH_I _ _ _ _ _ ...I I
RESULT'LSHINRM
A REGISTER X REGISTER
Figure 4-10. Multiply and Add
NORMALIZE A AND X. Contents of A and X registers are arithmetically shifted left (see figure 4-11) until bit 15 of A register is not equal to bit 14 or until maximum shift count specified (Expression 2) is exhausted.
Exponent (count cell), addressed by Expression I, is a two's complement number which is decremented (incremented in two's complement) once for each shift until normalization occurs. Address of exponent may be direct
o
or indirect and occupies second word of double-word NRM instruction. No indication is given if arithmetic overflow occurs when exponent is decremented.
NRM instruction treats A and X registers as a combined 31-bit. plus sign, register.
OV is reset (= 0) if normalization occurs; otherwise it is set (= 1). In eith,:r case •. exponent will be d~remented once for each shift performed.
A full 31-bit normalize is performed if no instruction count (Expression 2) is specified. Otherwise. specified count will determine maximum shifts performed. A normalize operation with a count of zero (Expression 2) provides a test for normalization without affecting contents of A and X registers.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D/~I ----1..-..· t=1 ===-.::::::-.::::-..::::-...:::-_-~o
(LOST! A REGISTER X REGISTER
Figure 4-11. NRM Shift Path 4-17
4.4 STACK, DOUBLE WORD INSTRUCTIONS (LS1-2 only)
Stack instructions permit the programmer to enter or retrieve a full la-bit word from a stack. A stack is a group of continuous 1De1DOI'J locationa whOse length is variable up to 32,768 words. A stack is organized on a laat-in-first-out basis whereby the last word entered into the stack will be the first word retrieved from the stack.
A stack can start at any address and ft11s from upper memory toward lower memory (decreasing addresses). The stack instructions themselves do not provide any stack boundary limit testing features. The user must provide boundary limit testing as overhead .saociated with using Stack instrucdons.
All stack accesees are controlled by a stack pointer for each stack. The stack pointer is a IS-bit address which points to the most recently accessed location in the stack.
The contents of the stack pointer are referred, to as the stack element addreu--SEA.
The stack pointer may be located anywhere in Memory •
Stack instructions occupy two consecutive worela in memory and opera$e in Word mode only. independent of proce8801' status. The first word contains the instruction whUe the second word contains the address of the stack pointer. The format for Stack instructions is shown below in figure 4-12.
With the stack pointer and the stack pointer addresa. indirection is not possible since the Processor ignores bit 15. If bit 15 of the stack pointer is a I, the stack pointer will be treated as a negative number when indexing (see paragraph 4.4.1.2) .
OPCODE OPERAND [.AII]
AM = No Operator
=
Direct AccessPUSH (stack pointer decremented prior to access) + POP (stack pointer incremented after access)
e
Indexed (single level)Figure 4-12. Stack Instruction Format
The Label and Comment fields are optional with this class of instruction.
The Op Code fteld must be present. The legal op codes for Stack instructions are defined in paragraphs 4.4.2 through 4.4.6 inclusive.
The Operand field consists of one or two expressions. The first expression represents a memory address and must be present. The second expression (AM) is optional and, when included, must be separated from the first by a comma. This expression represents the addressing mode of the Stack instruction. Figure 4-12 gives a list of valid expression characters and their associated addressing modes, and 4.4.1 describes them in greater detail.
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COMMa AU'IOMAJION.INC.
BD
These instructions generate two IS-bit words. The first word is the Stack instruction Op code. The second word is the absolute address of the stack pointer.
4.4.1 Addressing Modes (Figure 4-l3)
To provide Oexibility in stack management. four addressing modes are provided with Stack instructions.
4.4. 1.1 Direct Access to Stack
In the Direct Access mode. the second word of the instruction (stack pointer address --SPA) is used to fetch the stack pointer from Memory. In this mode. the stack pointer contains the etfective stack element address (SEA) and is used to access the stack element for entry. retrieval. or testing of data.
4.4.1.2 Indexed Access to Stack
In the Indexed Access mode. the SPA in the second word of the instruction is used to fetch the stack pointer from Memory. The contents of the signed X register are then algebraically summed with the stack pointer to form-the effective SEA. After the summation, bit 15 is treated as a 0 for accessing the stack element. This allows access to the nth element in the stack relative to the last stack entry when the X register contains n. For example. if X =0. the most recent stack entry is accessed while if X = 1. the next most recent entry is accessed.
4.4. 1.3 Auto-Posfincrement Access to Stack (POP)
In the Auto-Postincrement mode. the SPA is used to obtain the stack pointer. In this mode. the stack pointer contains the effective SEA and provides direct access to the stack element. Upon completion of the stack access. the stack pointer is incremented and restored to its memory location. This mode of addressing appears to remove (POP) the most recent entry from the stack when used with a load type instruction.
4.4.1.4 Auto-Predecrement Access to Stack (PUSH)
In this mode. the stack pointer is accessed via the SPA. decremented by one. and restored. The stack element is then accessed using the decremented contents of the stack pointer. This mode of addressing appears to insert (PUSH) a new entry onto the stack when used with a store type instruction.
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COWUTER AUTOMATION. INC.
· ·
·
Full Full
STACK INSTRUCTION-OPCODE
P
STACK POINTER P+1 ADDRESS ~
Full
---..t
STACK POINTER- I SEASPA STACK ELEMENT - Full
I Empty
Empty
-Steck Pointer Always Points to Most Recent Entry in Stack.
Empty Empty
· · ·
Figure 4-13. Stack Organization and Management
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--"-
.-:7FFF
SEA+n
t
UPPER MEMORY
POP SEA + 1
1
SEA
SEA·l SEA· 2 PUSH
LOWER MEMORY
SEA·n
-1
:0000
4.4.2 Arithmetic Stack Instructions
ADDS ADD STACK ELEMENT TO A. Adds contents of stack element to contents of A register. OV is set if arithmetic overflow occurs.
SUBS SUBTRACT STACK ELEMENT FROM A. Subtracts contents of stack element from contents of A register. OV is set if arithmetic overflow occurs.
4.4. 3 Logical Stack Instructions
ANDS AND STACK ELEMENT TO A. Logically AND's contents of stack element with contents of A register. Result replaces contents of A register.
IORS INCLUSIVE OR STACK ELEMENT TO A. Inclusively OR's contents of stack element with contents of A register. Result replaces conteJlts of A register.
XORS EXCLUSIVE OR STACK ELEMENT TO A. Ex~lusively OR's contents of stack element with contents of A register. Result replaces contents of A register.
4.4.5 Program Transfer Stack Instructions
CMSS COMPARE STACK ELEMENT TO A AND SKIP IF HIGH OR EQUAL. Compares contents of stack element with contents of A register. If A register is greater than contents of stack element. a one word skip OCCUl'S. If A register is equal to contents of stack element. a two word skip occurs.
IMSS
If A -register is less than contents of stack element. next sequential instruction is executed.
INCREMENT STACK ELEMENT AND SKIP ON ZERO RESULT. Contents of stack element are incremented by one. If increment causes result to become zero. a one word skip OCCUl'S. If not. the next sequential instruct-ion is executed. OV is set if arithmetic overfiow occurs.
JMPS JUMP UNCONDITIONAL. P register is loaded with contents of stack pointer (SEA). causing an unconditional branch to the addressed stack element location. Next instruction is executed from location SEA.
JSTS JUMP AND STORE TO STACK ELEMENT. Contents of P register (P + 2) are stored in stack element and P register is then loaded with address of stack element plus one (SEA + 1). Next instruction is accessed trom location SEA + 1.
4.4 . 6 Stack Control Instruction
SLAS STACK ELEMENT ADDRESS TO A. Loads contents of stack pointer into A
4.4.4 Data Transfer Stack Instructions register.
EMAS EXCHANGE STACK ELEMENT AND A. Simultaneously stores contents of A register 1.n stack element and loads contents of the stack element into A register.
LDAS LOAD STACK ELEMENT INTO A. Loads contents of stack element into A register.
LDXS LOAD STACK ELEMENT INTO X. Loads contents of stack element into X register.
STAS STORE A IN STACK ELEMENT. Stores contents of A register in stack element.
STXS STORE X IN STACK ELEMENT. Stores contents of X register in stack element.
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