Segment Override Prefixes. General register BX and pointer register BP may serve as base registers. When BX is the base the operand by default resides in the current Data Segment and the DS register is used to compute the physical address of the operand. When BP is the base the operand by default resides in the current Stack Segment and the SS segment register is used to compute the physical address of the operand. When both base and index registers are used the operand by default resides in the segment determined by the base register, i.e., BX means DS is: used, BP means SS is used. When an index register alone is used, the operand by default resides in the current Data Segment. The physical address of most other memory operands is by default computed using the DS segment register (exceptions are noted below).
These assembler-default segment register selections may be overridden by preceding the referencing instruction with a segment override prefix.
Description: The segment register selected by the reg field of a segment prefix is used to compute the physical address for the instruction this prefix precedes. This prefix may be combined with the LOCK andlor REP prefixes, although the latter has certain requirements and consequences-see REP.
En~oding:
10 0 1 reg 1 1 0
I
reg is assigned according to the following table:
Exceptions: using the SS segment register, which may not be overridden. The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden.
Register Operands: The four 16-bit general registers and the four 16-bit pointer and index registers may serve interchangeably as operands in nearly all 16-bit opera-tions. Three exceptions to note are multiply, divide, and some string operations, which use the AX register implicitly. The eight 8-bit registers of the HL group may serve interchangeably in 8-bit operations. Multiply, divide, and some string opera-tions use AL implicitly.
Description: Register operands may be indicated by a distinguished field, in which case REG will represent the selected register, or by an encoded field, in which case EA will represent the register selected by the rim field. Instructions without a "w"
bit always refer to 16-bit registers (if they refer to any register at all); those with a
"w" bit refer to either 8- or 16-bit registers according to "w" .
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Encoding:
REG is assigned according to the following table:
16-Bit [w = 1] a-Bit [w = 0] FLAGS to represent the file:
FLAGS X:X:X:X:(OF):(DF):(lF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF) where X is undefined.
Immediate Operands. All two-operand operations except multiply, divide, and the string operations allow one source operand to appear within the instruction as im-mediate data. Sixteen-bit imim-mediate operands having a high-order byte which is the sign extension of the low-order byte may be abbreviated to eight bits.
Three points about immediate operands should be made:
• Immediate operands always follow addressing mode displacement constants (when present) in the instruction.
• The low-order byte of 16-bit immediate operands always precedes the high-order byte.
• The 8-bit immediate operands of instructions with s:w
=
11 are sign-extended to 16-bit values.Below each type of instruction, the following information is given:
1 . A descriptive English name or phrase 2. The instruction's binary encoding
3. The time it takes, expressed in clock cycles (using a 5-MHz clock, one cycle is 200 nanoseconds; using an 8-MHz clock, one cycle is 125 nanoseconds)
4. A step-by-step operational description
5. A list of flags set to 1 or reset to 0 during the operation of this instruction (see also Appendix C).
6. A general description of when the instruction is used, how it works, defaults it may use or invoke, and points to remember about its interaction with other in-structions or directives.
7. Examples
The times given for instructions depend on the nature of the operands. These times are fixed for register-to-register operations and for immediate-data-to-register operations, e.g.
MOV OX, AX takes 2 cycles
MOV OX, 444 takes 4 cycles, regardless of which register or what data.
Operands in memory take some extra time for calculating the Effective Address.
These added cycles are indicated in the listed times by the term "+ EA". The amount of time needed varies depending on 3 factors:
a. Which addressing mode was used in the address expression for the memory operand.
b. Whether a segment override prefix byte is needed.
c. For word operands, whether the first byte of the word resides at an even or odd address.
The list below shows the added cycles needed for each addressing mode to access either 8-bit memory operands or 16-bit memory operands (words) whose first byte is at an even address. Add 4 cycles for words residing at odd memory addresses. Add 2 cycles if a segment override is used.
1.
indirect through base or index register e.g., MOV
ex,
[SX]MOV
ex,
[SI]each takes 8
+
5 or 13 cyclesindirect through base or index register with displacement constant
e.g., MOV OX, SIMPLE_NAME [SX]
MOV SIMPLE_NAME [01]
ex
each takes 8 + 9 or 17 cycles
indirect through sum of one base and one index register e.g., MOV DX, [SX] [SI]
MOV [SX] [01] ,
ex
each takes 8 + 7 or 15 cycles
indirect through sum of base and index register plus displacement constant expres-sions involving that variable would require 4 extra cycles. If a segment override were necessary (see ASSUME in Chapter 4), then an additional 2 cycles must be added.
Thus the instruction MOV ES:SIMPLE_NAME, CX would require 16 instead of 14 cycles, and 20 cycles if the first byte of SIMPLE_NAME were at an odd address.
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