SECTION 5 • REGISTER DESCRIP'I'IONS
5.1 Device Control Register Descriptions
SECTION 5 Register Descriptions
SO CHIP RESETIPOWER·DOWN CONTROL REGISTER (SOh, RIW, CRPCTL)
7 (RIW) (lDDQTST) - DISABLE ALL PULL-UPS: When set, this bit disables the internal pull-up resistors for all signal pins that use pull-up resistors.
6 (RIW) Reserved
5 (RIW) (DBLKPDN_EN) - DISK BLOCK POWER-DOWN ENABLE: When set, this bit allows the Disk block to turn off clocks to circuits that do not require them at the current time. The clocks are automatically enabled as needed. When this bit is reset, the Disk Control block is powered up and various internal disk related circuits are clocking as required. This bit is internally synchronized so that the internal clock does not glitch when being powered up or down.
4 (RIW) (BBLKPDN_EN) - BUFFER BLOCK POWER-DOWN ENABLE: When set, this bit allows the Buffer block to turn off clocks to circuits that do not require them at the current time (except for the DRAM refresh logic, which is powered down via the RAM Select bits RAMSEL[2:0], reg. lOOh, R/W, bits 5-3). The clocks are automatically enabled as needed.
When this bit is reset, the Buffer Control block is powered up and various internal buffer related circuits are clocking as required. This bit is internally synchronized so that the inter-nal clock does not glitch when being powered up or down.
3 (RIW) (HBLKPDN_EN) - HOST BLOCK POWER-DOWN ENABLE: When set, this bit allows the Host block to turn off clocks to circuits that do not require them at the current time. The clocks are automatically enabled as needed. When this bit is reset, the Host block is pow-ered up and various internal host related circuits are clocking as required.
2 (RIW) (DBLKRST) - DISK BLOCK RESET: When this bit is set, the Disk Control block and the ECC block are initialized to their reset state. This bit is latched to a 1 by the occurrence of Power-On Reset (*POR), and it remains latched until a 0 is written to it.
1 (RIW) (BBLKRST) - BUFFER BLOCK RESET: When this bit is set, the Buffer Control block is initialized to its reset state. This bit is latched to a 1 by the occurrence of Power-On Reset (*POR), and it remains latched until a 0 is written to it.
o
(RIW) (HBLKRST) - HOST BLOCK RESET: When this bit is set, the Host block is initialized to its reset state. This bit is latched to a 1 by the occurrence of Power-On Reset (*POR), and it remains latched until a 0 is written to it.Ale-837S Data Sheet Confidential
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Register Descriptions SectionS
51 CHIP MODE REGISTER (51h, RIW, CMODE)
7 (RIW) (HADSBLPU) - DISABLE HOST ADDRESS PULL-UPS: When set, this bit disables the internal pull-up resistors for the HA[2:0] input pins.
6 (RIW) (HCDSBLPU) - DISABLE HOST CONTROL PULL-UPS: When set, this bit disables the internal pull-up resistors for the Host control (*PDIAG and *DASP) I/O pins.
5 (RIW) (SWAPREG) - SWAP REGISTER ADDRESSES: When this bit is set, certain two and three byte registers that are accessible by the microprocessor will have their addresses swapped so that the MSB will have a lower address than the LSB. This is useful for word access using Motorola type microprocessors. When this bit is reset, the LSB will have a lower address than the MSB, which is useful for word access using Intel type microprocessors.
4 (RIW) (BDDSBLPU) - DISABLE BUFFER DATA BUS PULL-UPS: When set, this bit disables the internal pull-up resistors for the BD[15:0] signal pins.
3 (RIW) (ENPPRDY) -ENABLE PUSH-PULL READY: When set, this bit configures the READY pin for push-pull operation. When cleared, the READY pin operates in open drain mode.
2 (RIW) (COMBINT) - COMBINE ALL INTERRUPfS: When set allows the disk interrupts to be OR'd into the INTIlBD pin. When cleared, the disk interrupts create an interrupt only on the INTDpin.
(RIW) (ENPPINT) - ENABLE PUSH-PULL INTERRUPf OUTPUTS: When set, this bit config-ures the INTHBD and INTO signal pins as push-pull signals. When cleared, INTHBD and INTO are configured in the open drain mode.
o
(RIW) (ACTHI1NT) - ENABLE ACTIVE HIGH INTERRUPf OUTPUTS: When this bit is set, the INTHBD and INTO interrupt signals to the microprocessor will be active high. When this bit is reset, INTHBD and INTO will be active low.52 CHIP STATUS (52h, R, CSTAT)
7 (R)
6:5 (R)
(BUSYMA) - BUSY FOR MICROPROCESSOR ACCESS: This bit is set whenever the AIC-8375 is busy completing a previous microprocessor access to the buffer RAM or a syn-chronous write or read register. When the READY signal to the microprocessor is not being used, the microprocessor should check this bit after it accesses the buffer RAM or certain synchronous registers to make sure that the access has internally been completed before next access is started. On buffer read accesses, this bit is cleared after data has been latched into the 'register to data bus' latch, i.e., at the negation of *MOE or *RAS.
(DISKINT[1 :0]) - DISK INTERRUPT ACTIVE[1 :0]: These two bits reflect the OR'd status of the two Disk Interrupt Status registers. DISKINT[I] will be set as the OR'd condition of any enabled interrupt status bit currently set in the Disk Interrupt 1 Status register (reg. 66h, R). DISKINT[O] will be set as the OR'd condition of any enabled interrupt status bit cur-rently set in the Disk Interrupt 0 Status register (reg. 5Eh, R).
SectionS
4:3 (R)
2:0 (R)
Register Descriptions
(BUFINT[1:0]) - BUFFER INTERRUPf ACTIVE[1:0]: These two bits reflect the OR'd status of the two Buffer Interrupt Status registers. BUFINT[l] will be set as the OR'd condi-tion of any enabled interrupt status bit currently set in the Buffer Interrupt 1 Status register (reg. 106h, R). BUFINT[O] will be set as the OR'd condition of any enabled interrupt status bit currently set in the Buffer Interrupt 0 Status register (reg. l03h, R).
(HOSTINT[2:0]) - HOST INTERRUPf ACTIVE[2:0]: These three bits reflect the OR'd status of the three Host Interrupt Status registers. HOSTINT[2] will be set as the OR'd con-dition of any enabled interrupt status bit currently set in the Host Interrupt 2 Status register (reg. E4h, R). HOSTINT[1] and HOSTINT[O] apply in an identical fashion to the Host Interrupt 1 Status (reg. CAh, R) and the Host Interrupt 0 Status registers (reg. C8h, R) respectively.
S3 CHIP INTERRUYf ENABLE (S3h, RIW, CINTEN)
7 (RIW) Reserved
6:5 (RIW) (EN_DISKINT[1:0]) - ENABLE DISK INTERR UPf[1 :0]: These two bits enab~e either one or both of the Disk Interrupt Active bits (reg. 52h, R, bits 6:5) to generate an interrupt to the local microprocesor via the INTO pin (and possibly the INTIIB pin - see reg. 5Ih, RIW, bit 2). EN_DISKINT[1] will enable DISKINT[l] (reg. 52h, R, bit 6) to generate an interrupt.
EN_DISKINT[O] will enable DISK1NT[O] (reg. 52h, R, bit 5) to generate an interrupt.
4:3 (RIW) (EN_BUFINT[l:O]) - ENABLE BUFFER INTERRUPf[1 :0]: These two bits enable either one or both of the Buffer Interrupt Active bits (reg. 52h, R, bits 4:3) to generate an interrupt to the local microprocesor via the INTHBD pin. EN_BUFINT[l] will enable BUFINT[1]
(reg. 52h, R, bit 4) to generate an interrupt. EN_BUFINT[O] will enable BUFINT[O] (reg.
52h, R. bit 3) to generate an interrupt.
2:0 (R/W) (EN_HOSTINT[2:0) - ENABLE HOST IN1ERRUPf[2:0]: These three bits enable the corresponding Host Interrupt Active bits (reg. 52h, R, bits 2:0) to generate an interrupt to the local microprocesor via the INTIIBD pin. EN_HOSTINT[2] will enable HOSTINT[2] (reg.
52h, R, bit 2) to generate an interrupt. EN_HOSTINT[1] and ENHOSTINT[O] enable HOSTINT[1] and HOSTINT[O] to generate interrupts in a similar fashion.
54 CHIP REVISION REGISTER (S4h, R, CREV)
7:0 (R) (REVNUM) -PART REVISION NUMBER: The value in this register reflects the revision status of the AIC-8375. The revision number for the AIC-8375 is 'OOh'. The number will be incremented by' lh' for any subsequent revisions of the device.
55 CHIP TEST REGISTER (55b, RIW, CTEST)
The bits in this register are intended only for manufacturing test of the AIC-8375 device.
7 (RIW) (DHIZ) - DISK INTERFACE HIGH IMPEDANCE MODE: When this bit is set, all of the Disk Interface output signals will be forced to the high-impedance state.
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Register Descriptions SectionS
6 (RIW) (BHIZ) - BUFFER INTERFACE HIGH IMPEDANCE MODE: When this bit is set, all of the Buffer Interface output signals will be forced to the high-impedance state.
5 (RIW) (HHIZ) - HOST INTERFACE HIGH IMPEDANCE MODE: When this bit is set, all of the Host Interface output signals will be forced to the high-impedance state.
4 (RIW) (VTHTESn - INPUT THRESHOLD VOLTAGE 1EST: When this bit is set, all of the bi-directional pins of the AIC-8375 will be forced into a high impedance state. The INTD pin will become the output from the VTH test NAND chain whose inputs are driven by all the input and bi-directional pins (except *POR).
3 (RIW) (VOTEST) - OUTPUT VOLTAGE TEST: When this bit is set, all of the output and bi-direc-tional pins will be configured as outputs. The output level is determined by one or more user selected input pins.
2:0 (RIW) (TES1MODE[2:0]) - STANDALONE TEST MODE SELECT[2:0]: For manufacturing use only. These bits should be left at '0' for normal operation.
Section 5 Register Descriptions