4. Field Programmable Gate Arrays (FPGAs)
4.5. Deployment 2: Signal Processing in Heterodyne Systems
Figure 4.12: Long-term scan verifying the proper mode of operation of the FPGA photon counting module. Deviations from the set value are caused by a mismatch of the two quartz oscillators in the FPGA as well as the arbitrary function generator and demonstrate the importance of using a common and accurate 10 MHz clock.
4.5. Deployment 2: Signal Processing in Heterodyne Systems
The processing of heterodyne data in real-time poses a far more demanding challenge than in the photon counting case before. So far, real-time evaluation of the data was only possible by the help of analog components. The physical principle of the heterodyne detection itself will be explained in Chapter 5.6. For now, it is sufficient to keep in mind that the heterodyne signal is the mixed optical field transmitted through the cavity. The optical frequency is down-converted by an optical local oscillator from 384 THz to a radio-frequency of around 25 MHz.
A separate FPGA is dedicated to process the data coming from the heterodyne detection. Due to the more complex data treatment and higher requirements concerning the data-transfer to the host PC, a NI FlexRIO PXIe-7966R board equipped with the more advanced Xilinx Virtex-5 SXT95 (-2) is employed. In this device the computation is facilitated by the large number of embedded DSP-slices (digital signal processing), while the 4x lane PCI-express interface guarantees transfer-rate close to 1 GB/sec. To maintain high through-put rates even while storing files, a NI HDD-8265 raid array (configured in raid-mode 6) is used.
4.5.1. Direct Digital Synthesis of Radio Frequencies
The generation of RF-signals by means of DDS (direct digital synthesis) is very prominent18 in this thesis. Hence, it is worth to quickly describe the underlying principle. The frequency is adjusted by an integer value called frequency tuning word (FTW). We will assume the case where it is N-bit wide, as it is depicted in an overview in Figure 4.13 a). On every clock cycle
18 Besides the commercially available DDS-chips which are used to provide a frequency for the AOM drivers, this frequency synthesis is also used to demodulate the heterodyne signal, to compute the beat frequency of the cavity as well as to compute the parametric feedback.
0 20 40 60 80 100 120 140 160 180
-0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20
Monday, 2009-06-15 00:00 Tuesday, 2009-06-16 00:00 Wednesday, 2009-06-17 00:00 Thursday, 2009-06-18 00:00 Friday, 2009-06-19 00:00 Saturday, 2009-06-20 00:00 Sunday, 2009-06-21 00:00 Monday, 2009-06-22 00:00
periode deviationt/T-10ppm (ppm)
time (hours)
Field Programmable Gate Arrays (FPGAs) 4.5 Deployment 2: Signal Processing in Heterodyne Systems
an integer counter is increased by the FTW. In case its maximum value of 2N – 1 is surpassed, an arithmetic overflow occurs, which is disregarded and the accumulation is carried on as shown in Figure 4.13 b). This is identical to taking the current value modulo 2N. The integer range of the counter hence can be mapped to the interval from 0 to 2p. This signal of the counter thus corresponds to the phase of the generated frequency. As shown in part a) a sine-LUT, which is simply a sine curve stored in the memory, achieves the fast angle-to-amplitude conversion.
Figure 4.13: Working principle of a direct digital synthesis (DDS). a) Every clock cycle an internal counter is raised by the value of the FTW. The value of the counter corresponds to the phase of the generated frequency and is fed into a sine LUT.
This outputs an M-bit wide sine wave. b) Visualization of an overflow occurring while iteratively adding the FTW to the counter. The vertical axis shows the maximal value range of the counter and the horizontal axis depicts the clock signal.
Assuming that the clock is running at the sampling rate fs, the frequency output by the DDS routine fDDS is given by the FTW. Its desired value can be determined by
round 2N DDS
Employing this DDS routine, all local oscillator frequencies inside the FPGA are generated, supporting frequencies from as low as fS 2N up to the Nyquist frequency fS 2.
4.5.2. Real-time Processing of the Heterodyne Carrier
The heterodyne signal, which is centered around 25 MHz, is sent to the FPGA system. There it is sampled by the NI-5781 adapter module. The sampling rate of this module is set to
s 100
f = MHz with a resolution of 14-bit. Additional Bessel filters at the input, bandwidth-limit the data to 40 MHz. The now digitalized signal is passed to the pins of the FPGA for an actual processing of the data stream.
An overview of the processing is depicted in Figure 4.14. In the beginning, the data stream is multiplied with a local oscillator, which converts it to the complex baseband19. The local
19 The term complex baseband refers to a signal compromising an in-phase and a quadrature phase component. It is the same as working with a complex number, where one component is the real part and the other the imaginary one.
4.5 Deployment 2: Signal Processing in Heterodyne Systems Field Programmable Gate Arrays (FPGAs)
oscillator is produced by an internal DDS generator. The FTW is 32-bit wide. A frequency of 25 MHz hence corresponds to an FTW =230. The multiplication is performed twice in parallel, once with the unshifted local oscillator (in-phase; I component), and once with a 90-degree delayed local oscillator (quadrature-phase; Q component). These two components pass a variable moving average low-pass filter, whose frequency response can be controlled via the LabVIEW front-panel. Afterwards, they are converted to an amplitude and phase information, which is subsequently used for the feedback-logic as well as output by a DAC and displayed on a VGA screen.
The transfer of data to the host PC is achieved by a direct-memory-access (DMA). Two DMA channels are used. One is responsible to directly transfer the 14-bit RAW data generated during the digitization20. The other one takes the digitally down-converted (DDC) data, decimates21 it by a variable factor M and then bitwise joins the 16-bit wide I/Q component into a single 32-bit wide signal. The selected data stream is then saved onto a RAID-array which guarantees a sustainable write rate of more than 600MB/sec. The RAW data permits to reconstruct the full bandwidth of the signal and has the heterodyne carrier at its original frequency. The data after
20 The transfer uses a 16-bit wide data channel. The remaining two bits are hence free to be used for additional control information. This is e.g. done during the switching measurement (c.f. 6.7).
21 Decimation means to reduce the data rate of data stream by a certain factor M. Adjacent M samples of the original stream are averaged and output as one sample.
RF Heterodyne Signal converter (ADC), it passes a 40 MHz lowpass filter (LP). The digital signal is multiplied with a local oscillator (LO) and its -90-degree phase-shifted facsimile. This down-mixes the signal and shifts the heterodyne carrier to DC frequency. The two components (I/Q) subsequently pass a set of variable low-pass filters before they are converted to an amplitude (r) and phase () information. The amplitude information is used by the feedback routine and is also output as an analog output. The VGA screen in addition also displays the phase information of the carrier. Data is transferred in two ways to the host PC, either as raw data or as digitally converted data (DDC). The latter one is derived by sending the two components of the down-mixed signal through a pair of decimators and combining these two signals bitwise to have one common data stream.