DBEN HIBYTE

RiW

m ^{m ill} m ^ill m

.JJ \\\ m \\\ ^~

JJ \\\ m \\\ ---1l1

--11l ^ill HI u\

---1JJ'"---ill m ^ill m

~

~ ========================================:========

DBEN HIBYTE DTACK l5Tt

ClK

\\\

m \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\111 \\\

HI m

- - i - - - W r i t e - - - - + - - Bus Idle --+----Write Retry to Device

Retry Asserted

0/

\\\ m m m

(NOTESI ^{11 In the _ ~mptory bus} exception. the bus cycle should always terminate irnrned~ly. but norm .. ty; i.e. it should IIquenaI

off • if • DTACK had _n rKei~

38

21 In the _ of • R~MAC should not tarminata the c:ycte until the BEe pins h _ been stable in title Retry c:odI for at s..t

one dock. even if • DTACK is also rec::eiwd.

31 See the bus exception commenu below the Halt d~

Figure 40 Retry Operation

eHITACHI

•

! ill

,.

,

..

..

I

..

.. ..

III

III

•

•

•

•

•

•

•

• ! -,.

..

•

- - - H D 6 8 4 5 0 - 4 . H D 6 8 4 5 0 - 6 . H 0 6 8 4 5 0 - 8

CLK

J

AiD BUS

::::xw

UAS

~ , _~

AS J ^\ r

" ^{I ~}

UDS

J ^{\ r--'} ,.., I

'-LOS

J , I '

" ^{I \.}

R/W

,

I

OWN

~

lmm \\ I' ,..., ~

DBEN \\ ,--..

^I

_\\ ^/I

HIBYTE \ I

DTACK

---'I USSUS~i.muunny , ^,

0'fC

~

At"K

" ^{I \ r\..}

RlINQ-

msms~~ UI

SGACK I' ,

BR

\ ^I

m;

CLK

--4----Read----oI-Other Read

Retry-'----Relinquish and Retry Master and

Asserted Rearbitration

• BEC;-nc, -

Relinquish.net Retry Code

(NOTES) 1) In the c.e~plOry bus exception. the bus cycle thould . . . , . w.nnindl immed~. Iv. but norrNIlv; i.e. it thould .-quence off. if a OTACK hm been rKeNed.

2) In the c:.a of a Relinquish and Retry. the DMAC should not tarmiMte the cycle until the

IR

pins " -been stable in the Relinquish .net Retry code for at ' - t two clocks. awn if a ~ ill allo ...-iwd.

3) See the bus exception comments below the Haft di.-m.

Figure 41 Relinquish and Retry Operation

eHITACHI 39

r ..

H 0 6 8 4 S 0 4 . H 0 6 8 4 S 0 6 . H 0 6 8 4 S 0 8 ,

-He

CONTROLS

If the

HEr

controb

are

&llerted to a state that is undefmedl reserved. this venion of the DMAC wiD enter a wait state and

resume

operation when the exception is removed.

(3) ERROR CONDITIONS

Enumerated below are the error signals and their source~.

ConfJgUration Error confJgUntion will signal a confIgUration error. The undefmed confIgUrations are: XPM =01, MAC = 11, DAC = 11, CHAIN

=

01. SIZE = 11.

Operation Tuning Error

An operation timing error is signaled if an attempt is made to continue an operation without STR being simultaneously set or if the channel is not active. Oper:ation timing error is and ACT are asserted.

Address Error

Address error is signaled if an odd address operation is at-tempted with word or long word operands or if

CS

or

lACK

^is

asserted while the DMAC is bus master. The address error is asserted after the odd address is encountered. this is consistent with the processor operation.

BusEnor con-tinue or chain processing.

Abort

An abort error is signaled if the

PCL

line was confIgUred as an abort input and made an active transition, or if the channel operation

was

aborted by the

SAB

bit of the CCR.

Note: When the

PCL

line is used as an abort input, the PeT bit should be cleared prior to starting the channeL If the

PCT

bit is set prior to the channel being started, the DMAC will recogllize this as an external abort when the channel is started.

When the transfer mode is set to dual addressing mode. the transfer direction is set to I/O device to mem-ory, and

PCL

signal is set to external about input mode,

the external abort for that channel will be .nored after ~ ~ a

DONE

input from the I/O device is receiVed during the thannel's I/O device-to-t1'M~mory data transfer cycle.

After the DONE input. the dwmel wiU accept external ~ abort when the channel is properly reinitialized and is ~ restarted. _ )( _

ERROR RECOVERY PROCEDURES

If an. error occurs during a DMA

transfer,

appropriate infor-mation is available to the operatilllg system to allow a "soft failure"' operation. The operating system must be able to determine how much data

was

transferred, where the data

was

transferred to, and what type of em.r occurred.

The information available to the operating system consists of the present values of the Memory Address, Device Address and Base Address Registers, the Memory Transfer and Base T~s-fer Counters, and control. status, and error registers. After the successful completion of any transfer, the memory and device address registers points to the location of the next operand to

to the entry being fetched. II

MULTIPLE ERRORS X II

The DMAC wiD log the fust error encountered in the channel

III

error resister. If an error is pending in the error register and another error is encountered the second error will not be logged.

This is true in the case of an error pending and an attempt is ~ made to set the STR bit. In this C3lOC the Operation timing error ~ is not logged in the error register but the error is recognized intemaDy and the channel is not started.

c

• CHANNEL PRIORITIES

Each channel has a priority level, determined by the contents of the Channel Priority Register (CPR).

The

priority of a chan·

JIll

requesting channels at the highest priority level, a round-robin resolution is used, that is, as long .IS these channels continue to have requests, the DMAC does oper.md transfers in rotation. ~

• APPLICATIONS INFORMATICIN

..

This section contains examples of how to interface various 1/0 devices to a HMCS68000/DMAC based system.

f"

Figure 42 shows an example of how to demultiplex the ad· -.

dress/data bus.

Figure 43 indicates the exampll~ of how to latch the data, ~

when the DMAC

has

two channels which operate in 6800 mode. ^I Figure 44 indicates the example of inter-device connection

II

in the HMCS68000 system.

40

^eHITACHI

..

•

..

•

•

•

..

III

III

III

III

III

.. ^~ III

- - - HD68450-4.HD68450-6.HD68450-8

Yo •

Vi<

!Wtii lAS 0.-0.,.

AI-A ..

Hoea.50 ISRlII

GImI

OMA CONTROlLEII

1741.SOlI

L--:J

Vee Vee

....-~

I III

21 ^AI-AD 7 ... 537)

7 ... 52 . . 0.-0.

E II

741.5245 0.-0 ..

C£

Dill

Figure 42 Required Multiplexed Data/Address Hardware for the Bus Control Logic

J

i

! I

i r

I

_i

^I

_!

,

~

I I

I

I

V

1 u

D.-D~

_T_

^1&1

o... r

-A4-Au . / - Cf

r=-o-odIor

Ai L - - - III _E

I

o.-D~

_T_

o..;.

..--A,-Au . / - 8

~ o-odIor liS

AS l...- E

I

ACK; ^AS

~ ~

~ ^{r- me;}

^{~~ ~ RJii HDIIC60}

-'

^{I DMAC}

6E t:.

G 74LS373

,

^...

_M

D. -D~ ./ ^ID -CD ^lQ '1Q 0.--0. ) .... 'lYe

~

-y 8US - ~1IlDti CONTROL

LOGIC

D.-Oil " rF . . ,.421 .... -A ..

Figure 43 An Example of Connection with Peripheral Devices in 6800 Mode

• HITACHI 41

H D 6 8 4 5 0 4 . H D 6 8 4 5 0 · 6 . H D 6 8 4 5 0 · 8

Memory Control Unit

AS

RC' Peripheral

lAS _____

^{t - - -}

^...

PI!ripheral LSI R/IN

f

-E

11m

'"-Figure 44 An Example of Jnter~vice Connection in the HMCS08000 System

• HITACHI

Im Dokument MANUAL CC-74 DMA-SCSI INTERFACE MODULE (Seite 194-198)