Daughter-card interface

The aim of the daughter-card interface is to provide hardware designers with all the unused resources of the StrongARM SA-1100 processor [DEC98b] and UCB1200 analog interface [Phi97b]. Daughter-cards are connected to the Itsy mother-board through a 160-pin connector. The functionality available through the daughter-card interface includes:

2 static-memory banks (banks 2 and 3). It is possible to boot from the daughter-card. In this case, bank 0 mirrors bank 2.

3 DRAM banks (banks 1, 2 and 3).

2-socket Personal Computer Memory Card International Association (PCMCIA) interface.

4 serial interfaces: universal serial bus (USB), universal asynchronous receiver/transmitter (UART), synchronous data link controller (SDLC), and synchronous serial port (SSP).

15 general-purpose input/output signals, 13 of which can be used for interrupts.

1 telecommunication codec (e.g., for software modem).

1 general-purpose analog input (10-bit analog-to-digital converter, nominal voltage range:

[0V^::7^:5V]).

Not all these features are available simultaneously, since three of the serial interfaces (i.e., UART, SDLC, SSP) are allocated by reconguring some of the general-purpose input/output pins.

Table 4 shows the pin-out of the daughter-card connector. Some signals (mostly the memory bus) are buered by SN74LVCH16244ADGG drivers [TI97a] or SN74LVCH16245ADGG trans-ceivers [TI97b]. Buered signals are explicitly specied as such in the description below. All other signals are unbuered. All buers are enabled when the signal ^GPIO19 (^DCEN) is set to 1 and disabled when it is set to 0 (see Section 3.2). The following signals are available:

The Itsy Pocket Computer Version 1.5: User's Manual

On the Itsy mother-board version 1.1, pin 158 is connected to ground (^GND).

Table 4: Daughter-card connector pin-out.

The Itsy Pocket Computer Version 1.5: User's Manual

GND

: g

rou

nd

27 pins are used to carry the system's ground.

P3300

: p

ower

3

.

300

V

24 pins are used to carry the 3.3V-nominal power-supply voltage ^Vdd (see Section 2.2). The amount of current available to daughter-cards varies depending on the processing state of the Itsy computer (i.e., CPU core frequency, enabled/disabled state of all units, etc.). Daughter-cards that do not draw more than 80mA while the StrongARM SA-1100 processor [DEC98b]

is in sleep mode, and do not draw more than 200 mA while the processor is in idle or run modes, can be accommodated in almost any processing states. A further power analysis, beyond the scope of this document, is required to accommodate daughter-cards that require more current.

PWRIN

: p

o

w

e

r in

put

3 pins are used to carry the unregulated battery voltage^Vpwrin (see Section 2.2). The amount of current available to daughter-cards varies depending on the processing state of the Itsy computer (i.e., CPU core frequency, enabled/disabled state of all units, etc.).

DCRST

: d

aughter-

c

ard

r

e

s

e

t

On the Itsy mother-board version 1.5, this output signal is asserted (0) during a hardware reset (i.e., power-up or push-button reset). It corresponds to the input signal ^RESET of the StrongARM SA-1100 processor [DEC98b] buered by an SN74LVCH16244ADGG driver [TI97a] (see Section 2.3).⁶

RESET OUT

: reset out

put

This output signal is asserted (0) during a reset (i.e., hardware, software, or watch-dog reset) and during sleep mode. It is directly connected to the corresponding pin of the StrongARM SA-1100 processor [DEC98b].

PWR EN

: p

o

w

e

r en

able

This output signal is asserted (1) during run mode or idle mode and de-asserted (0) during sleep mode. It is connected directly to the corresponding pin of the StrongARM SA-1100 processor [DEC98b].

DCBOOT

: d

aughter-

c

ard

boot

select

This input signal denes whether a daughter-card is bootable or not. It is sampled after a hardware reset (i.e., power-up or push-button reset) or while exiting sleep mode. If, at sampling time, this signal is asserted (0) and the signal ^GPIO19 (^DCEN) is set to 1, static-memory bank 0 mirrors bank 2 and the StrongARM SA-1100 processor [DEC98b] boots from the daughter-card. Otherwise, static-memory bank 0 mirrors bank 1 and the processor boots from the mother-board. A pull-up resistor keeps this signal de-asserted (1) by default.

After a hardware reset, the boot memory is solely selected by the signal^DCBOOT, since the value of the signal^GPIO19 (^DCEN) is always 1 (see Section 3.2). The signal^DCBOOTis not

6On the Itsy mother-board version 1.1, the signal ^DCRST does not exist and pin 158 is connected to ground ( ).

The Itsy Pocket Computer Version 1.5: User's Manual

sampled after a software or watch-dog reset, because the processor does not sample the signal

ROM SELafter these types of reset.⁷

DCROMSEL

: d

aughter-

c

ard boot

ROM

width

sel

ect

This input signal denes the width of static-memory bank 2 on a bootable daughter-card.

A value of 0 corresponds to a 16-bit bank, while a value of 1 corresponds to a 32-bit bank.

A pull-up resistor sets the default value of this signal to 1. This signal is used to set the signal^{ROM SEL}of the StrongARM SA-1100 processor [DEC98b] when static-memory bank 0 mirrors bank 2 (see signal^DCBOOTabove).

DCCS

3::2

: d

aughter-

c

ard static-memory

c

hip

s

elect

These output signals control the accesses to the static-memory banks 2 and 3. The signal

DCCS

2 is generated directly by the PZ3032-8BC PLD [Phi97a] and is asserted when the signal ^CS2 of the StrongARM SA-1100 processor [DEC98b] is asserted or when the signal

CS

0 is asserted and static-memory bank 0 mirrors bank 2 (see signal^DCBOOTabove). This signal is enabled when the signal ^GPIO19 (^DCEN) is set to 1 and disabled when it is set to 0 (see Section 3.2). The signal ^DCCS3 corresponds to the signal ^CS3 buered by an SN74LVCH16244ADGG driver [TI97a].

DCRAS

3::1

: d

aughter-

c

ard DRAM

r

ow-

a

ddress

s

trobe

DCCAS

3::0

: d

aughter-

c

ard DRAM

c

olumn-

a

ddress

s

trobe

These output signals control the accesses to the DRAM banks 1, 2, and 3. They correspond to the signals^RAS3::1 and ^CAS3::0 of the StrongARM SA-1100 processor [DEC98b] buered by an SN74LVCH16244ADGG driver [TI97a].

DCOE

: d

aughter-

c

ard static-memory and DRAM

o

utput

e

nable

DCWE

: d

aughter-

c

ard static-memory and DRAM

w

rite

e

nable

These output signals control the accesses to the static-memory banks 2 and 3 (in conjunction with the signals^DCCS3::2) and to the DRAM banks 1, 2, and 3 (in conjunction with the signals

DCRAS

3::1 and ^DCCAS3::0). They correspond to the signals ^OEand ^WEof the StrongARM SA-1100 processor [DEC98b] buered by an SN74LVCH16244ADGG driver [TI97a].

DCPSKTSEL

: d

aughter-

c

ard

P

CMCIA

s

oc

k

e

t sel

ect

DCPREG

: d

aughter-

c

ard

P

CMCIA

reg

ister select

DCPCE

2::1

: d

aughter-

c

ard

P

CMCIA

c

hip

e

nable

DCPOE

: d

aughter-

c

ard

P

CMCIA

o

utput

e

nable

DCPWE

: d

aughter-

c

ard

P

CMCIA

w

rite

e

nable

DCPIOR

: d

aughter-

c

ard

P

CMCIA

i

nput/

o

utput

r

ead strobe

DCPIOW

: d

aughter-

c

ard

P

CMCIA

i

nput/

o

utput

w

rite strobe

These output signals control the accesses to the PCMCIA interface. They correspond to the signals^PSKTSEL,^PREG,^PCE2::1,^POE,^PWE,^PIOR, and ^PIOW of the StrongARM SA-1100 processor [DEC98b] buered by SN74LVCH16244ADGG drivers [TI97a].

7On the Itsy mother-board version 1.1, the signal^DCBOOTis also sampled after a software or watch-dog reset, hence, leading to potential problems when using a 16-bit daughter-card and allowing the value of the signal^DCBOOT to change.

The Itsy Pocket Computer Version 1.5: User's Manual

DCIOIS16

: d

aughter-

c

ard PCMCIA

i

nput/

o

utput

is 16

-bit wide

DCPWAIT

: d

aughter-

c

ard

P

CMCIA

wait

These input signals provide feed-back from the PCMCIA interface. They correspond to the signals ^IOIS16 and ^PWAIT of the StrongARM SA-1100 processor [DEC98b] buered by an SN74LVCH16244ADGG driver [TI97a]. Pull-up resistors keep the signals^IOIS16 and^PWAIT de-asserted (1) when the driver is disabled.

DCA

25::0

: d

aughter-

c

ard

a

ddress

These output signals implement the daughter-card address bus. They correspond to the address bus ^A25::0 of the StrongARM SA-1100 processor [DEC98b] buered by two SN74LVCH16244ADGG drivers [TI97a].

DCD

31::0

: d

aughter-

c

ard

d

ata

These bi-directional signals implement the daughter-card data bus. They correspond to the data bus ^D31::0 of the StrongARM SA-1100 processor [DEC98b] buered by two SN74LVCH16245ADGG transceivers [TI97b].

UDCP

: U

SB

d

evice

c

ontroller

p

ositive data

UDCN

: U

SB

d

evice

c

ontroller

n

egative data

These bi-directional signals implement the USB interface. They are directly connected to the ^UDC+ and ^UDC, pins of the StrongARM SA-1100 processor [DEC98b]. No protection circuitry is provided.

RXD 1

: r

eceive

d

ata, serial port

1

TXD 1

: t

ransmit

d

ata, serial port

1

These bi-directional signals can be used to implement the SDLC or UART engine of serial port 1 or can be congured as general-purpose input/output signals, as shown in Table 5.

They are directly connected to the corresponding pins of the StrongARM SA-1100 processor [DEC98b].

GPIO

27::25;18::10;1

: g

eneral-

p

urpose

i

nput/

o

utput

These bi-directional signals can be used as general-purpose input/output signals, as interrupts, or to implement their alternate function, as shown in Table 5. They are directly connected to the corresponding pins of the StrongARM SA-1100 processor [DEC98b]. It should be noted that the signal ^GPIO1 can be used to wake up the processor after a hardware transition to sleep mode due to the assertion of the signal ^{BATT FAULT} or the signal ^{VDD FAULT} (see Section 2.2.1).

TINP

: t

elecommunication

in

put

p

ositive data

TINN

: t

elecommunication

in

put

n

egative data

TOUTP

: t

elecommunication

out

put

p

ositive data

TOUTN

: t

elecommunication

out

put

n

egative data

These input and output signals implement the telecommunication codec (i.e., for software modem). They are directly connected to the corresponding pins of the UCB1200 analog interface [Phi97b].

The Itsy Pocket Computer Version 1.5: User's Manual

Main/alternate function Gen.-purp. signal

Signal Function Dir. Dir. Int. Sleep

RXD 1 Serial port 1 SDLC/UART receive data I I/O N Z, 0

TXD 1 Serial port 1 SDLC/UART transmit data O I/O N Z, 0

GPIO

Table 5: Daughter-card general-purpose input/output signals. The \sleep" column describes the possible sleep-mode states, the symbol \Z" means that the corresponding pin is congured as input.

DCAD

: d

aughter-

c

ard general-purpose

a

nalog-to-

d

igital input

This signal is a general-purpose analog input (10-bit analog-to-digital converter, nominal voltage range: [0V^::7^:5V]). It is directly connected to the ^AD3 pin of the UCB1200 analog interface [Phi97b].

Daughter-cards are intended to form or replace the back of an Itsy computer. Systems with only a small number of thin components can be entirely packaged on the top side of the daughter-card PCB and, hence, t in entirely in the case. On the other hand, systems that require more space can grow arbitrarily large on the bottom side of the daughter-card PCB. By sanding o the thin lip on the rear of the case, it is also possible to design daughter-card PCBs that are larger than the case. The mechanical specications of daughter-cards is provided in Appendix A.

2.7.1 Static-memory identication scheme

To allow self-conguration, the software should be able to determine if a daughter-card is used or not and, if present, it should be able to recognize the daughter-card. A few resources available on the daughter-card (e.g., the DRAM banks) can be detected without any additional hardware, but this is not the case for most devices. Moreover, it is sometimes useful to only partially as-semble a daughter-card (e.g., on a memory-extension daughter-card, only some of the available static-memory or DRAM banks may be present). In order to merge these requirements with the

The Itsy Pocket Computer Version 1.5: User's Manual

need to recognize which ash-memory circuits are used on the mother-board (see Section 2.5.1), a static-memory identication scheme|identical for all four static-memory banks of the StrongARM SA-1100 processor [DEC98b]|has been dened. Any daughter-card, using either static-memory bank 2 or 3 or using any otherwise undetectable resources (e.g., ^GPIO signals), should conform to this convention.

Several criteria were considered in the design of this mechanism:

This scheme should be compatible with both 16-bit and 32-bit static-memory banks. That is, the conguration software should recognize a given device without prior knowledge of its width.

Since the processor's endianess is programmable, this scheme should be dened independently of the current endianess.

The amount of additional hardware should be minimized.

To meet these goals, each possible static-memory device should implement an 8-bit class identica-tion register ^CID. Since there are only 256 possible values for this register, they should be assigned parsimoniously. Therefore, each value represents a class of devices (e.g., a single value is used for any non-volatile memory). Additional information, dened on a class basis, may be implemented to discriminate between dierent members of a class.

The address of the ^CIDregister should be xed and easily decodable. The rst word of a bank is not a good candidate, since this is the location of the reset vector in the boot static-memory bank. The rst address following the exception vectors is not a good candidate either, since this is typically the position of the fast interrupt request (FIQ) handler routine. Hence, the last word of a bank has been adopted as the address for the ^CIDregister.

This leads to the following convention: each static-memory device should decode a read access at address^A25::0 = 3

FFFFFE

¹⁶, with address bit^A0 ignored on a 16-bit device and address bits^A1::0 ignored on a 32-bit device. The device should then provide the 8-bit class identication value^CID on the data bits^D7::0. Partial address decoding (or even no decoding) may be used as appropriate.⁸ The class identication value ^CID= 255 =

FF

¹⁶ is reserved and will not be assigned to any static-memory device. With this knowledge, the conguration software can detect the absence of any device on a given bank, by driving the value 255 =

FF

¹⁶ on the data bits ^D7::0 before reading the bank's^CID register (the hardware is designed such that the last value driven on the data bus is preserved in the absence of any device driving the bus).

The class identication value^CID= 0 is assigned to any non-volatile memory, that is, read-only memory (ROM) or ash memory.⁹ Additional information for this class is dened in Section 3.3.

The^CIDregister as well as all additional information can be simply programmed in the non-volatile memory. On many daughter-cards, it may be useful to implement a non-volatile memory for general

8Although only the 26 least signicant address bits^A25::0 are available on the pins of the StrongARM SA-1100 processor, a 128Mbyte address space is internally allocated to each static-memory bank. Therefore, the oset of the

CIDregister within the static-memory bank is a 27-bit value with address bit^A26 being ignored.

9For the purpose of the conguration software, it is only useful to distinguish whether a non-volatile memory can be programmed in-circuit or not. Therefore, programmable ROM (PROM) and erasable programmable ROM (EPROM) are lumped in the ROM category. Likewise, electrically-erasable programmable ROM (EEPROM) are lumped in the ash-memory category.

The Itsy Pocket Computer Version 1.5: User's Manual

use in addition to some other hardware (e.g., serial interface, sensors). In order to generalize the conguration software, any such static-memory device should be assigned a class identication value ^CID127 = 7

F

¹⁶ (i.e., ^CID7= 0) while any other device should have a class identication value ^CID>128 = 80¹⁶ (i.e., ^CID7= 1). Devices of the rst category should implement the same additional information as non-volatile memories with the class identication value ^CID= 0 (see Section 3.3).

The mother-board ash memory, implemented as static-memory bank 1, conforms to the same identication scheme, with the class identication value ^CID= 0. Daughter-cards using static-memory banks 2 and 3 should implement both^CID registers. Daughter-cards that do not use any static-memory bank but use other resources should dedicate one or both banks to the identication scheme. In this case, the^CIDregister could easily be implemented using an 8-bit buer.

3 Programmer's model

This section presents additional information on the model that the low-level software has of the Itsy hardware.

3.1 Memory map

The internal decoding of the StrongARM SA-1100 processor [DEC98b] provides a general template as how the address space is used. Table 6 shows the memory map implemented by the Itsy computer. The rst column give the address range at which a particular device is decoded. The

\location" column species whether this device is internal to the processor, is implemented on the mother-board, or whether its interface is available to the daughter-card interface. Finally, the last two columns give the device's width and size (or possible widths and sizes, when several dierent devices can be implemented).

As mentioned in Section 2.5, static-memory bank 0|from which the processor boots|mirrors either bank 1 or bank 2 (see Sections 2.4, 2.7, and 3.2).

All DRAM banks must have 2¹² rows, as imposed by DRAM bank 0 (see Section 2.5.2). This limits the size of banks 1, 2, and 3 to 16Mbyte maximum (i.e., the largest size supported by the processor without external hardware). Using dierent DRAM circuits, 4Mbyte and 8Mbyte banks can also be implemented. Smaller banks can be considered as well. However, they are mapped in a non-contiguous address space.

Im Dokument WRL Technical Note TN-54 The Itsy Pocket Computer Version 1.5 User’s Manual (Seite 17-24)