SYSTEM ABSTRACT
The Sobit R6600microcomputer system is produced with N-Channel. Silicon Gata technology. Its performance speeds are enhanced by advanced system architecture. This innovative architec.ture results In smaller chips - the semiconductor threshold to cost .. ffectivity. System cost-effectivity is further enhanced by providing a family of 10 software<omp.tible microprocessor (CPU) devices. described in this document. Rockwell also pro-vides memory and microcomputer system ... as well as low<ost design aids and documentation.
R6500 MICROPROCESSOR (CPU) CONCEPT Ten CPU devices are available. All are software<ompatible.
They provide options of addressable memory. interrupt input.
on-chip clock oscillators and drivers. All are .t1us-compatible with ea.rlier generation microprocessors like the M6800 devices.
The family includes six microprocessors with on-board clock oscillators and drivers and four microprocessors driven by external clocks. The on-chip clock versions are aimed at high performance.
low cost applicetion. where single phase inputs. crystal or RC inputs provide the time baie. The external clock versions are geared for multiprocessor system applications whera maximum timing control is mandatory. All R6600 microprocessors are also available in a variety of packaging (ceramic and plastic).
operating frequency (1 MHz and 2 MHz) and temperature (com-mercial. industrial and militery) versions.
MEMBERS OF THE R6500 MICROPROCESSOR (CPU) FAMILY
Microprocessors with On-Chip Clock Oscillator Modal
AcIdr-a.1e Memory 65K Bytes
Microprocessors with External Two Phase Clock Output Model
• N channel. silicon gate. depletion load technology
• Eight bit perallel proceSSing
• 66 Instructions
a Decimal and binary arithmetic a Thirteen addressing model
• True indexing capability
• Programmable steck pointer
• Variable length stack
• Interrupt cepability
• Non-meskable Interrupt
• Use with any type of speed memory a Sobit Bidirectional Data Bus
• Addressable memory. range of up to 66K bytes
• "Ready" input
• Direct Memory Access capability
• Bus compatibla with M6800
• 1 MHz and 2 MHz operation
• Choice of external or on-chip clocks
• On·the-chip clock OPtions External single clock input - RC time base i/!PUt - Crystal time base input
• Commercial. industrial and military temperatura versions
• Pipeline arch itecture
Ordering Information Dreier Number: R66XX __ _
M" MIL-8TD.a83.
Class B C - Ceramic
P - Plattit (Not A\teible for M or MT suffix) F,.quency Range:
No suffix" 1 MHz A" 2 MHz Model Designator:
xx- 02.03.04 .... 15 NOTE: Cont.:t your local Rockwell Repre.ntati.,.
I =
-Clocks 1/1)" /l)2t·
The R651X requi .... a two ph ... non-overlapplng clock that runs at the V CC voltllllllievel.
The R650X clocks ate supplied with el'! internal clock generator.
The frequency of thlll clock. Is externelly controlled.
AddrlllBu.IAO-A15t
. These outputs ere TTL compatlble~ capable of driving one standard TTL load end 130 pF.
Data au, loo-O.7t
Eight pins ere used for the deta bu.. This is a bidirectional bus, transferring date to and from the device .nd peripherals. The out-puts .ret,l .. t.t. buffers cap.ble of driving one st.nd.rdTTL load and 130pF.
o.ta au. Enable (DBE)
This TTL compatible input allows extern.1 control of the tri .. tate dete output buffers and will enabla the microprocessor bus driver when In the high st.te. In normal operation DBE would be driven by tha phasa two 1/1)2) clock, thus ellowing data output from mlcroproc .. soronly during /1)2' During the read cycle, the date bus drivers .re Intem.lly disatiled. becoming .... ntl.lly an open circuit. To dl .. ble d.te bu. drivers externally, DBEshould be. held low.
Reedy IRDYt
This input sign.1 allows the usa, to helt or single cycle the micro-processor on all cycles except write cycl... A negetive trensition
• to the low state during or coincident with phase one 1/1)11 will halt the microprocessor with the output address lines reflecting the current eddress being fetchad. If Ready is low during a write cycle, it is ignorad until the following read operation. This con-dition will remain through a subsequent phese two (/1)2) in which the Ready signal is low. This feature allows microprocessor inter-, facing with the low speed PROMinter-, as well as fast (max. 2 cycle)
Direct Memory Access (DMA).
. Interrupt Rllquest liRQ)
This TTL level input requ .. ts that an interrupt sequence begin within the microprocessor. The microprocessor will complete the current instruction being exe.cuted beforarecognizing the request.
At that time. the interrupt mask bit In tha Status Code Register will be ex.mined. If the interrupt mask flag is not set, the micro-processor will begin an interrupt sequance. The Program Counter and Processor Status Register are stored in the stack. The micro-processor will then sat the intarrupt mask flag high so that no fur-ther interrupts may occur. At the end of this cycle. the program counter low ""ill be loaded from address FFFE. and program counter high from location F F F F. therefore transferring program control to the memory vector located at these addresses. The ROY signal must be in the high. state for any interrupt to be rec-ognized. A 3Kn external resistor should be used for proper wire-OR oper.tion.
Non Masl.1e In ... pt lAllI),
A negative !!Ding edge on this Input requlStslhat • non"",aslcable interrupt sequence be gener.ted within· the microprOcessor.
AUI is an unconditlon.1 interrupt. FolfQwing completion of the current instruction, the sequence of operations daflned for iRa
will be performed, regerdless of the state Interrupt mask flag, The veCtor address loaded Into the p~ogram counter. low end high, ere locations FFFA and FFFB respectiVely, thereby transferring pro-gram control to the memory vector loc.ted .t th.sa addresses.
The Instructions loaded .t these locations c.usa the
mlcroproc-·essor to branch to a non""'askable interrupt routine In mirnory.
NMI also requires .n externel 3K n regis,ter t~ V CC for pl'oper
wire-OR operations. .
Inputs iFiQ and NMI are hardw.re interrupts. lines that .re .. Status Code Register. This Signal is samplad on the trailing edge of /1)1 and must be e)!ternally synchronized.
SYNC goes high. In this manner, the SYNC slgn.1 can be used to control ROY to cau .. single instruction execution.
R ....
This input is used to reset or start the microprocessor from • power down condition. During the time that this line is held low.
writing to or from the microprocessor is inhibited. When a posi-tive edge is detected on the input, the microprocessor will imme-diately begin the reset sequence.
After a system initialization time of six clock cycles, the mask interrupt flag will be set and the microprocessor will load the pro-gram counter from the memory vector locations FFFC and FFFD.
This is the start location for program control.
After V CC reaches 4.75 volts in a power up routine, reset must be held low for at le.st two clock cycles. At this time the R/W.nd (SYNC) signal will become valid.
When the resat signal goes high followingthel8 two clock cycles, the microprocessor will proceed with the normal re .. t procedure detailed above.
(
(
(
ADDRESSING MODES
ACCUMULATOR ADDRESSING - This form of addressing is represented with II one byte instruction. implying an operetion on the accumulator.
IMMEDIATE ADDRESSING - In immedillte addressing. the operllnd is contllined in the sacond byte of the instruction. with no further memory addressing required,
ABSOLUTE ADDRESSING - In abIolute addressing. the-second byte of the instruction specifies the eight low order bits of the effective eddress while the third byte speciflll the eight high order bits. Thus. the absolute add, ... ing mode allows ecCIII to the entire 65K bytes of eddrell8ble memory.
ZERO PAGE ADDRESSING - The zero page instructions Illow for shorter code Ind execution times by only fetching the second byte of the instruction Ind lllsuming II zero high address byte.
Camful use of the zero page Clln result in .ignificant incre . . in code efficiency.
INDEXED ZERO PAGE ADDRESSING - IX. Y indexing) - This form of addressing il used in conjunction with the index register lind is referred to lIS "Zero Page. X" or "Zero Page, Y". The effec-tivlI address is clliculated by adding the second byte to the con-tents of the index register. Since this is a form of "Zero Page"
addressing. tho content of tho second byte references I location in page zero. Additionelly due to the "Zero Page" addressing nlture of this mode. no cerry is added to the high order 8 bits of memory and crossing of page boundlries does not occur.
INDEXED ABSOLUTE ADDRESSING - IX, V indexing) - This form of addressing is used in conjunction with X and V index reg-ister and is referred to III "Absolute, X",and "Absolute, V". The effective address is formed by adding the contents of X or Y to the address contained in the second and th ird bytes of the instruc-tion. This mode allows the index register to contein the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields relulting in reduced coding and execution time.
IMPLIED ADDRESSING - In the implied addressing mode. the address containing the operand i. implicitly stated in the operation code of the instruction.
RELATIVE ADDRESSING - Relltive addrealng il used only with branch instructions and esteb! Ishes I dlltlnetion for the con-ditional branch.
The second byte of the instruction becomes the operand which Is an "Offset" added to the contents of the 1 _ eight bits of the program counter when the countlr is set It thl next Instruction.
The range of the offset il -128 to + 127 bytes from thl next instruction.
INDEXED INDIRECT ADDRESSING - In indexed Indirect addressing Ireferred to III IIndirect. XII. the sacond bytl of the instruction Is added to the contents of the X index regilter. dis-carding the clrry. The result of this addition points to I memory location on page zero whose contents I. the low order eight bits of the effective add,.... The next memory location in page zero contlins the high order eight bits of the effective address. 80th memory locetions specifying the high Ind low order bytes of the effective address must be in page zero.
INDIRECT INDEXED ADDRESSING - I.n indirect indexed addressing lreferred to lIS Undirectl. VI. the second byte of the instruction points to a memory locltion in page zero. The con-tents of this memory location is added to the concon-tents of the V index register, the result being the low order eight bits of the effective address. The carry from this eddition is added to the contents of the next page zero memory locltion. tile result being the high order eight bits of the effective address.
ABSOLUTE INDIRECT - The second byte of the instruction contains the low order eight bits of II memory locltion. The high order eight biu of that memory locetion is contained in the third byte of the instruction. The contents of the fully specified mem-ory location is the low order byte of the effactive add,.... The next memory location contains the high order byte of the effec-tive address which is loaded into the sixteen bits of the progrem counter.
INSTRUCTION SET - ALPHABETIC SEQUENCE
ADC Add Memory to Accumulator with Carry JMP Jump to New location
AND "AND" Memory with Accumulator JSR Jump to New location Saving Return Address ASl Shift laft One Bit (Memory or Accumulator)
lOA load Accumulator with Memory
8CC Branch on Carry Clear lOX load Index X with Memory
CLI Clear Interrupt Disable Bit RTI Return from Interrupt
ClV Clear Overllow Flag RTS Return from Subroutine
CMP Compare Memory and Accumulator SBC Subtract Memory from Accumulator with Borrow
CPX Compare Memory and Index X SEC Set Carry Flag
CPY Compare Memory and Index Y SED Set Decimal Mode
SEI Set Interrupt Disabla Status
DEC Decrement Memory by One STA Store Accumulator in Memory
DEX Decrement Index X by One STX Store Index X in Memory
DEY Decrement Index Y by One STV Store Index Y in Memory
1/11 (OUT)
iFiQ N.C.
NMi SYNC VCC AO
A1 A2 A3 A4 A5
A6 A7 AS A9 A10 A1l
1/12 (OUT) S.D.
1/10 liN) N;C.
N.C.
R/Vi DO 01 02 03
04
05 06 07 A15 A14 A13 A12 VSS
Feetures of R6502
• 65K Addressable Bvtes of Memory IAO-A15)
• IRQ Interrupt
• On-the-chip Clock
TTL Level Single Phase Input RC Time Base Input Crystal Time Base Input
• SYNC Signal
Ican be used for single instruction execution)
• ROY Signal
lean be used to halt or single cvcle execution)
• Two Phase Output Clock for Timing of Support Chips
• NMI Interrupt
(
(
(
INSTRUCTION SET
A002TO N IF BRANCH OCCURS TO DIFFERENT PAGE
A ACCUMULATOR , AND n NO. CYCLES
131 CARRY NOT = BORROW
..
MEMORY PER EFFECTIVE ADDRESS v OR • NO. ByTES,"
<112 (OUT)
1/>,
15
[
REF "A" REF "0" REF " A ' (
PCH
"V6 UV
f--PWH<II 2=:}-;;0&-REF "0"
~f
O.4V LREF "A"
R/W
ADDRESS FROM CPU
DATAFROM __ ~ ______ 4-____ ~~ __ ~~
MEMORY
ROY. S.O.
SYNC
Clock Timing - R6512,13, 14, 15 Timing for Writing Data to Memory or Peripherals
. iREF"A"
....
, .. .0,---T eye - - - < . . . . j
7
I
A7
[ y
7
I
X7
I
PCl8 7
11 I
SRIW
ADDRESS FROM CPU
DATAFROM __ ~~ __________ ~ ____ ~~
CPU
TMDS-t---...
REF "8"
Note: "REF," means Reference Points on clocks,
PROGRAMMING MODEL
0 7 o
:oJ
ACCUMULATOR A INlvl IBIDlllzlcl PROCESSOR STATUS REG 'P"0
I
INDEX REGISTER Y0
L
CARRY 1 = TRUEJINDEX REGISTER X ' - - ZERO 1 = RESULT ZERO
0
• ] PROGRAM COUNTER "PC" IRQ DISABLE 1 = DISABLE
:::J
0 STACK POINTER "s'" DECIMAL MODE 1 = TRUEBRKCOMMAND 1 = BRK
OVERFLOW 1'" TRUE NEGATIVE 1 = NEG.
(
(
ADDRESS BUS
REGISTER SECTION CONTROL SECTION ---1~~
r-
~ +~
w INSTRUCTION
~ 2. AddreSSing Capability and control options vary with each
of the R6S00 Products.
ROY
(
DOCUMENT NO. 29000047 REVISION 1. OCT. 1978
PART NUMBER