{ Power to PROM
RD/WRT DATA ENABLE
FIGURE 7-1
UPP-872 PERSONALITY CARD BLOCK DIAGRAM
PROM CS/ SOCKET I
1---11---=---+1 ON
VEB FRONT I
PANEL I
VCC
PROM READ/WRITE DATA LOGIC
t-3 o
There are five major components of the UPP-872 Personality Card shown in Figure 7-1:
1) The Address Boundary Check Logic examines the l2-bit PROM Address from the Control Board. Since the l702A PROM is organized into 256 words, the address must be within the range of 0 to 255 (i.e., the four most
significant bits must be zero). If the address is out of this range the logic will signal the address error at port 9, bit 1, of a 4001 ROM (,A14).
2) The Address Inverter and Level Shifter receives the PROM Address from the Address Boundary Check Logic and transforms i t into the type of signal required at the address pins of the PROM. The input V-Address determines whether the address is inverted (comple-mented) or not. The input VCC determines the voltage level of the PROM address.
3) The Two Intel® 4001 ROMs are a part of the MCST.:,M40 (the processor itself is located on the Control Board) . The ROMs contain instructions for the MC~Y40 that will effect the reading or programming of a l702A PROM.
The MCS~~O interacts with the Personality Card through the I/O ports on the two ROM chips.
4) The Voltage Regulator and Programming Pulse Circuits develop the pulses that are required to program the PROM. These circuits receive commands from the ROM I/O ports and supply the appropriate voltages to the PROM. The major source of power for the UPP-872 Persona-lity Card is the VCCP power line. In the read mode,
VCCP
=
5 VDC, which is generated from VCCH through a dropping diode. In the program mode, VCCP=
48 VDC.There are two protection provisions in the program mode.
One is a current limit which is set at approximately 700 mAe The other is a crow-bar which will fire if VCCP is greater than 56 VDC. If the crow-bar fires, the +70 VDC power is grounded through a 5n, 5 watt resistor which will cause the 1 Amp fuse, associated with the +70 VDC,
to blow. The Personality Card will return a hardware error
if a program operation is attempted & the + 70 VDC is not prelsent.
CAUTIO~ - It is possible to damage the regulator if the Personality Card is removed when the +70 volt line is not totally discharged. For this reason, a user must wait 60 seconds after system power is off before removing this Personality Card.
5) The PROM Read/Write Data Logic performs one of two functions. During a program operation i t accepts data from the PROM Write Data bus, and supplies i t to the PROM at the appropriate voltage level. During a read operation i t accepts data from the PROM and, if Data Enable is true, i t returns the data to the Control Board.
The remainder of this section will describe how these functional blocks interact to perform the two operations: program and read.
There are two distinct locations in the ROM on the UPP-872 Person-ality Card that are the entry points to which the MC~~~O branches:
one entry point for a program operation and one for a read. When the Personality Card receives control i t assumes that the PROM Address is available on the address bus. In the case of a program operation i t also assumes that the PROM Write Data is on the data bus. In either case the first step is to check for an address error.
The address check is simply a matter of testing the Address Error at the ROM input port. If this signal is true the selected address exceeds 255. If this occurs the Personality Card aborts the
operation and returns control to the Control Board. If the address is valid, the operation continues.
PROM READ DATA:
In the case of a read operation there is little left that needs to be done, since the static conditions of the Personality Card pre-sent the selected PROM data word to the PROM Read/Write Data Logic.
All the MCST~M40 needs to do is turn on the Data Enable line from the 4001 ROM (A14) output port 9, bit 3. When this is done the PROM
7-8
Read Data is returned to the Control Board. The Personality Card has then completed the read operation. Program control, then returnls to the Control Board.
PROM PROGRAM DATA:
~rhe Program operation is a bit more involved. After the address has been checked, the program operation begins. The sequence of events is as follows:
1) The MCS~~O checks to see that the Voltage Regulator is receiving +70 volts from the Power Supply_ If the signal PV Power from the Voltage Regulator to ROM (A14) port 9, bit 2 is true, then the +70 volts is available.
If not, the program operation is aborted, and control returned to the Control Board. (Hardware Error)
2) The signal RD/WRT is switched from low (which indicates read) to high (indicating program). This transition causes the following:
a) All six Voltage Regulator outputs are changed as shown in Figure 7-2.
b) The PROM Read/Write Data Logic inverts the Write Data and presents i t to the PROM as shown in Figure 7-2.
3) The signal V-Address is switched from low to high.
This causes the Address Inverter to complement each address bit. The complemented address is presented to the PROM as shown in Figure 7-2.
4) Approximately 110 11S lat:er, PVGG is swi tched from low to high. This causes VDD (pin 88) and VGG (pin 80) to drop as shown in Figure 7-28
5) Approximately 72 11S after that, V-Address is switched back to low causing the address to be presented to the PROM in true (non-inverted) form.
6) After approximately 72 11S, PVPRO switches from low to
high causing VPROG (pin 77) to dip as shown in Figure 7-2:.
PPROG VADDR PVGG PVPRO
VCC
VDD VGG CS/
VBB
VPROG
ADDRESS
DATA
~
r--so
,uSEe II~ n
PS
~---fltt~---~
II
\
\
\ 3.25 MSEC
\
\Sv
j
48V OV'21 I ~
~
IJSEC~'----"-l9Y,----~---t---2.9 JJSEC ' l + 4 8 V
~---r--~---+--- +12V
'--....:..9V.:..--_ _ _
3.25 MSEC
n
~_
-375.uSEC_~I-oI~,
,-' - - - ... 2.8 M S E C - - - - -.....-~~~
_ _ _I - -_ _ _ _ ~---~
II
FIGURE 7-2
VOLTAGE REGULATOR OUTPUTS TO SOCKET
UPP-872 PERSONALITY CARD: PROGRAM TIMING (ALL TIMES ARE APPROXIMATE)
7) The Personality Card now holds this condition constant for approximately 2.8 msec. Then PVPRO is switched back to low causing VPROG to rise.
8) After a delay of about 21 ~s PVGG is switched back to low, causing VGG and VDD to rise.
9) After another delay of 21 ~s RD/WRT is switched back to low causing all six Voltage Regulator outputs to drop back to their normal levels (these levels allow a read operation to be performed) .
10) The Personality Card now allows the PROM to "restn for approximately 12.5 msec. (Since a single program cycle requires about 3 msec., the duty cycle is
approximately 20%.)
11) After each program cycle the MCST.:.M40 performs a "read-after-write" compare using the comparitor logic on the Control Board. The Personality Card will attempt a maximum of 49 program cycles before returning control to the Control Board with a failure to program error.
After the Personality Card successfully programs a location i t will continue to program that same location for a number of cycles to insure against a marginally programmed word. If N attempts are required before the first successful program, an additional 4N+5 repetitions will be performed. Upon conclusion of these
repetitions, the PROM location is considered completely programmed and control returns to the Control Board.
7.3 PIN LIST: UPP-872 PERSONALITY CARD
The UPP-872 Personality Card communicates with the Control Board and the PROM socket on the front panel through a 100-pin double-sided PC edge connector. Pin allocations and designated signal functions for this IOO-pin connector are listed in Table 7-1.
TABLE
7-2UPP-872 PERSONALITY CARD PIN LIST