Arithmetic Section
The purpose of the arithmetic section is to perform arithmetic, comparisons, transfers of data, and other data manipulating operations.
The arithmetic section consists of an adder network and three arithmetic registers, which have one word (48-bit) capacities. The regis-ters are the accumulator (A Register)tthe data register (D Register), and the multiplier-quotient register
(0
Register). For floating point opera-tions, an optional unit is added to the basic section. \16·
The registers have the following functions:
a. D Register:
1.
rece1ves all data transferred between the memory and the arithmetic unit2. rece1ves all data transferred between arithmetic registers 3. contains the addend in addition, the subtrahend in
sub-traction, the multiplicand 1n multiplication, and the divisor in division
4. contains one of two factors 1n a compar1son
5. ...
--'
b. A Register:
ace ('5. S
-/-0
/ , \ "j IV:( ( . A1.
contains the augend in addition, the minuend in subtrac-tion, and the dividend or the more significant half of the dividend in division2. contains the sum in addition, the difference in subtrac-tion, the product or more significant half of the product in multiplication, and the remainder in division
3. contains one of two factors in a comparison
... J ~ !
f /, -"//- '.,
VL.{-, '" .r' I~_ ' I I I ',fJ I,",
) ) I., . Lt \,;.,...-':. \ "
! I
.. , ,'- / :
c.
Q
Register:1.
contains the multiplier in multiplication; the less sig-nificant half of a double length product of a multiplica-tion; the less significant half of a double length divi-dend in division; and the quotient of a division2. may contain a factor in a compar1son
3. con tains a masking pa t tern during an extracting opera tion.
, (' (Ji UIl:,) / I (.(
An arithmeticirrs-t:ruction is interpreted as a fixed point instruc-tion if the F bit is a zero. In the fixed point mode, the binary point of a data word lies immediately to the right of the sign or zero position as shown in the following diagram: (A description of floating point numbers will be found in Appendix E.)
I
0 [ 1I
2I 3 1 4 1)\ 143 144 1 45 146 14
71
~ Rinary Point TIle maX1mum positive number is
1
0 [
1 11111111111 11 11 11 11 I
f
WhiCh is less than one as far as the computer is concerned. Negative num-bers are represented in two's complement form, the smallest computernega-l,
tive number being minus oner; Any a,rithmetic result which would be outside the above limits produces accon~it~on called overflow.'"::>(1' "'o/ I , / ( 1"" t.' , J ' .~\;\: ~~(7/'J" ? . J ' 'j t /./" / ~'
I "
",),.'tt /"( ,J ( ' , , ' ) / •• ~) C)IUt' .:: IIndex Registers C;,// i·.i/~·:'·.·'(·",,/ J('I':'-:l~:) ..
Index registers in the 2000 operate in several ways, depending on the type of instruction using them. Their uses may be categorized as follows:
a. Instruction Address Modification: After an index register is filled by the desired address modifier, the effective address of the instruction using this register is the sum of the con-tents of the index register and the V field of the instruction.
Most PHILCO 2000 instructions can be address-modified in this manner, without altering the instruction in memory or the con-tents of the index register.
b. Counting: An index register may be set to automatically in-crease itself by one each time it is used. Used with an in-struction which doesn't utilize the V portion (such as an arithmetic register-to-register transfer), the index register will contain the total number of executions of the instruction.
Using the counting function for address modification permits consecutive memory locations to be addressed automatically.
17
c. Instruction Address Substitution: An address in an index register may replace an address part of an instruction in memory.
Input-Output Control
All input-output communication takes place between the magnetic core memory and the input-output units. Simultaneous computation and input-output operations are achieved by use of the Input-Output Processor, an Input-Output Register, and the special mode of operation described below.
Input data is collected in independent one-word registers in the Input-Output Processor or Paper Tape System while computation is in progress.
After a word has been collected, it is transferred to a one-word Input-Output Register in the Central Computer. The program is then interrupted so that
the word may be transferred, in parallel, to the core memory. During the transfer, the input unit is still in operation. After the transfer, the Central Computer resumes process1ng.
Output operations occur in a similar manner. The program is interrupted only when another word is required by the output unit. After the word has been transferred to the Input-Output Register, the program continues and the word is written or transferred to a buffer-controller simultaneously with the computer operation.
The Console Typewriter operates independently of the normal input-output circuitry.
TERMINOLOGY
The abbreviations of terms used 1n this manual excluding the mnemon1C codes are defined as follows:
TAC: Translator-Assembler-Compiler
PR:
The Program RegisterMA:
The Memory Address RegisterPA:
The Program Address RegisterJA:
The Jump Address Register 10: The Input-Output RegisterX: An index register
c: The counter indicator bit of an index register
M:
A memory location18
A: The A Register
Q:
The Q Register one-word registersD:
The D Register I: An instruction.The following letters may be used as subscripts with M, A, Q, D, and I:
L:
The left half of a wordn·
The right half of a wordV:
TIle variable field of an instruction F: The function bit of an instructionc:
The seven-bit command part of an instructions:
The index register selector bit of an instructionN:
The number of the index regis ter selected.Associated with X, the subscript, c, may be used; with
JA,
the subscript, F, may be used.
V-
I{-The following additional abbreviations are also used:
( ) : The contents of
1
I:
The absolute value of the contents of~: Is placed 1n
_.
Is equivalent to.( .O.J I,;\:ttl_,
ut\1
1,,' (' ((I. {-C.
(.1)- (-(-.(
C • ) "For example, the abbreviations listed have the following meanings:
DLV ==
the V part of the left half of (D)JA
F==
the F bit associated withJA
.::
I I"i\
',J>
1.,1"~ \
The contents of Index Register number
31
are equal to a V part of (D) ., I . '
\, 1 t ,; ( 1\
(\
!
( t t ;~" ... \
'J.-19
PAPER TAPE
HIGH- SPEED PRINTERS
INPUT-OUTPUT
MAGNETIC TAPE UNITS
CONSOLE TYPEWRITER
PAPER TAPE, REAL- TIME SCANNER, AND AUTO-CONTRQL
INPUT-OUTPUT PROCESSOR UNIVERSAL
BUFFER-CONTROLLER
MAGNETIC TAPE (OFF LINE)
MAGNETIC DRUMS
ARITHMETIC SECTION
MEMORY
PROGRAM SECTION
JUMP ADDRESS
MEMORY ADDRESS
CONTROL ADDER
INDEX REGISTER
SELECT
MEMORY PRESET
CONSOLE SWITCHES
PROGRAM ADDRESS
Figure 2. Simplified Diagram of the
PHILCO 2000System
YES STOP
CHAPTER III
INTRODUCTION TO CODING
TRANSFERS AND ARITHMETIC
In the previous chapter, the
PHILCO
2000 instruction was describ-ed in terms of its size and structure. It was seen that a binary instruc-tion code is very efficient for a machine. However, this code which is suitable to the computer is not convenient for programmers. Therefore, a completely functional English-decimal mnemonic code has been prepared for thePHILCO
2000. (The reader should be aware that from this point on the instructions described exist in the machine but not in the form shown here.The term" mnemonic instruction" is used to distinguish the code that the programmer writes from the" computer ins truction" or code tha t the computer accepts.) The mnemonic code, by itself, is unacceptable to the computer and cannot cause it to function. To enable the computer to operate, it is necessary to use a translation program. This program, the Translator-Assembler-Compiler (TAC) J converts the mnemonic code wri tten by the pro-grammer into the binary computer code.
The
PHILCO
2000 Mnemonic CodeThe
PHILCO
2000 mnemonic code has been designed to facilitate the learning and use of the computer instructions, which number over 200. This has been done by grouping the instructions into classes of computer opera-tions and then naming them mnemonically. Essential to data processing are the following instruction classes:a. addition
h.
subtraction c. multiplication d. divisione. transfer of data f. jump
g.
shiftingh.
extracting1. index register housekeeping J • input-output
k. special.
21
M~emonic Code Instructions
Just as a computer instruction has a command part and an address part, so does the mnemonic instruction. TIle command part of the instruc-tion is composed of two to six letters and is divided into three secinstruc-tions.
TIle command completely defines an operation in one of preceding instruction classes. It also specifies the origins of operands, the disposition of
For example, Addition instructions (fixed point mode) are compos-ed of the following letters: