by RICHARD L. PETRITZ
Texas Instruments Incorporated Dallas, Texas
I. INTRODUCTION
Considerable progress has been made in large scale il}tegration technology during the past year. Many of the goals, which were theoretical assumptions last year, are now well along the way to reality. Accom-plishments range from basic materials processing improvements to systems architecture innovations.
While this paper will concentrate on large scale in-tegration technology achievements, we shall also focus some attention on progress in significant re-lated areas.
The electronics industry has been relatively open with respect to large scale integration (LSI) in-vestigations, and much of the work has been, and con-tinues to be, presented at technical meetings and published in the literature. In addition, the U.S.
Air Force has under sponsorship a major program!
with three contractors2.:3.4 to develop LSI technology.
We shall make frequent reference to these reports and to the author's papers of 19655 and 1966.6 Reviewing the terminology which the author used in previous papers,5.6 we see LSI as a system of tech-nologies underlying the products which are called IECs (integrated electronic components). * The dis-tinction between "technology" and "product" is summar; zed in Table I for three generations of solid-state electronics. Table I shows "transistor" as the surviving product terminology of the second genera-tion of electronics technology, and lists some of the technologies. Similarly, "integrated circuits" is the surviving product terminology of the third generation.
As discussed in Ref. 6 a distinction should be made between "integrated circuits" (lC) and the produ.cts, namely, "integrated electronic components," (ICE)
*In reference 6, lEe was interpreted to mean "integrated equip-ment component." Because of the broad acceptance of the term
"integrated electronics" as the generic term of the industry in place of "microelectronics," we now prefer lEe to mean "inte-grated electronic component." Another term under consideration is integrated electronic device (I ED); however, we shall use I Ee in this paper.
65
that will result from large scale integration technology.
The principal distinction between an IC and IEC is that the latter is the result of interconnecting circuits within the structure, whereas an IC is the result of interconnecting devices within the structure. Figure I shows the distinction between device, integrated cir-cuit, and integrated electronic component.
IEC
INTEGRATED ELECTRONIC COMPONENT
Ie INTEGRATED CIRCUIT
DEVICE
Figure I - Pictorial view of integrated electronic component (I Ee), integrated circuit (I e), and semiconductor device
Another term that is being used to some extent is MSI (medium scale integration) along with LSI.
When used in the context of complexity level MSI is generally related to complexity levels of 10-100 cir-cuits, while LSI refers to complexity levels greater than 100 circuits.
At least three well-defined LSI technologies are under development:
LSI chip technology LS I hybrid technology LSI full-slice technology
66 Fall Joint Computer Conference, 1967
Table I. Technology - Producta
Generation of Technology TerminolOlY Product TermioolOl)' Electronics
2nd grown JIIDCUon Tr&D8iltor
alloy mesa planar bipolar MOB
3rd monolithic Integrated Circuit (lC)
hybrid thin film thick film
4th LSI technology Integrated Electronic
chip- Component (lEC)
hybrld-• interconnection of chlpa through use of film technologies
• customized wiring
The basic characteristics of these technologies are summarized in Table I, and Figure 2 illustrates Figure 2 - Pictorial view of large scale integration technologies.
The pictures represent compamble sizes
Because of confusion between the terms fixed pattern metalization, discretionary wiring and cus-tomized wiring, and the need for preciseness in their meaning, we will review these and related concepts.
First let us emphasize that we are discussing two classes of products, standard . and custom. The
term customized wiring (metalization) refers to a cus-tomized metalization pattern for a specific product.
Looking to the manufacturing process, we need to recognize two major technologies, fixed pattern metal-ization, and discretionary wiring (pattern) tion. The fixed pattern process uses the same metaliza-tion pattern from slice to slice in the manufacture of a specific product, whether it be a standard or a cus-tom product. For a cuscus-tom product, the fixed pattern metalization differs from product to product, but for the manufacture of a specific' product it remains the same.
Discretionary-wiring technology is a method of enhancing yield and' provides different metalization patterns for each slice in the manufacturing process, whether the product be standard or custom. A partic-ular advantage or the discretionary-wiring technology is that for many applications it accomplishes the cus-tomized-wiring function with relative simplicity. How-ever, in other applications this is not necessarily the case.
In summary, both standard and custom products can be manufactured with a fixed-pattern technology or with a discretionary-wiring technology, or a com-bination of both. In order to abbreviate terminology, we have defined on Table I chip technology to imply fixed pattern metalization, and full-slice technology to employ both fixed pattern metalization and dis-cretionary wiring. As will be discussed later, the rel-ative emphasis of fixed versus discretionary metaliza-tion varies for different full-slice technology lEes.
Progress will be reviewed in each of these technolo-gies as follows:
II LSI Bipolar Chip Technology III LSI Full-Slice Technology IV LSI MOS Technology
V LSI Hybrid Technology
Section VI develops the considerations of complexity (level of integration) versus cost, performance, and reliability for LSI technologies.
I I. LSI bipolar chip technology A. Review of Status of 1967 IC and
IEC Production Technology
The monolithic integrated circuit technology pro-cesses slices of silicon such as that shown in Figure 3a. The slice has been processed through metalization and is ready for probing. Each small area (chip or bar) on the wafer is probed, and the good and bad units are marked accordingly. The slice is then scribed into chips and the good chips in turn are assembled into packages and tested. Figure 3b shows a sequence of the silicon chip being assembled into a plastic package.
Current Status of Large Scale Integration Technology 67
la) Ib)
Figure 3 - a) Semiconductor slice showing metalized integrated circuit chip areas. The slice is ready for probing and then scribing into chips. (b) From left to right, fourteen lead metal frame without integrated circuit chip; the chip mounted in the lead frame; the plastic encapsulation has occurred; the completed integrated
circuit in a plastic package
Table II is a listing of some of the key characteris-tics of the Series 54 T2L line of integrated circuits.
The important points are the following: bar (chip) sizes average 2600 mil2; the devices per bar average 25; the area per device averages 104 mil2; the average number of circuits per package is 4; and the average area per circuit is 620 miI2. These averages include the effect of bonding pads. Line widths of 0.2 mil and spacings of 0.2 mil are used.
These data summarize modern slice processing technology. Integrated circuits of 1962-63 vintage would show one or two circuits per bar and the bars would be considerably larger. For example the early Series 51 designs used bar sizes 14,000 mil2 (70 mil x 200 mil) and contained one to two circuits. Line widths of 1 mil and spacings of 1 mil were used.
The industry recognized at least three years ago that four circuits were about all that could be eco-nomically placed in a single package if all gate (cir-cuit) leads needed to be accessible from the terminals.
Four circuits require 16 terminals, using 4 terminals per circuit. At the same time it was also reasonably clear that greater economics were ahead if more circuit function could be incorporated into a single package.
Thus the direction was taken toward interconnecting circuits within the chip, and this was the genesis of the integrated electronic component product line.
Table III lists the Series 54 T2L IECs that are now in production. Note that the average bar size is 7000 miI2; the average devices per bar is 124; the average area per device is 56 mil2; the average circuits per bar is 25; and the average area per circuit function is 280 mil2. By comparing these averages with those of Table II it is apparent that IECs are more effective than I Cs in utilizing the silicon area. Note the trend to larger bar sizes, with several approaching 10,000 mil2.
Table II. Series 54/74 T L Integrated Circuits (ICs) 2
Device Bar Size Bar Size
No. of Area/Device
No. of Area/Circuit
No. Circuit Type
(mn2) (mi12) Devices (mn2
) Circuits (mil2)
SN5400 Quad - 2 input gate 50 x 60 3000 36 83 4 750
SN5410 Triple - 3 input gate 50 x 60 3000 27 110 3 1000
SN5420 Dual - 4 input gate 45 x 45 2025 18 125 2 1012
SN5430 Single - 8 inIAlt gate 40x 40 1600 9 180 1 1600
SN5440 Power dual - 4 input gate 50 x 50 2500 22 114 2 1250
SN5450 Dual 2-wide 2 input AND-OR-Inv. E 50 x 55 2750 24 115 6 460
SN5451 Dual 2-wide 2 input AND-OR-Inv. 50 x 55 2750 24 115 6 460
SN5453 4-wide 2 inIAlt AND-OR-Inv. E 50 x 55 2750 18 153 5 550
SN5454 4-wide 2 inIAlt AND-OR-Inv. 50 x 55 2750 18 153 5 550
SN5460 Dual - 4 input Expander 35 x 40 1400 6 230 2 700
SN5470 J-K Flip-Flop 55 x 60 3300 56 57 8 400
SN5472 J-K Flip-Flop Master Slave 55 x 60 3300 40 80 6 535
--
-- -
--TOTAL
. . . . .
31,125 298-
50-Average
. .
2600 25 104 4.2 62068 Fall Joint Computer Conference, 1967
Table III. Series 54/74 T2L Integrated Electronic Components (IECs)
Bar Size Bar Area Area/Device
Equiva- Area/Gate
Device Function (mn2
) <mn2)
No. of
(mn2
) <mn2)
Devices" lent Gate
SN5441 BCD to Decimal Decoder/Driver 60 x 60 3600 50 72 17 212
SN5475 Quad latch 60 x 120 7200 120 60 24 300
SN5480 Gated full adder 65 x 65 4225 69 61 14 301
SN5482 2- Bit full adder 65 x 65 4225 83 51 21 200
SN5490 BCD decade counter 50 x 115 5750 102 56 18 320
SN5491 8-Bit shift register 55 x 110 6050 143 42 35 173
SN5492 Divide by 12 counter 50 x 115 5750 96 60 17 340
SN5493 Divide by 16 counter 50 x 115 5750 96 60 17 340
SN5494 Dual P.I., S.O. 4-Bit S.R. 70 x 110 7700 125 62 20 385
SN5496 P.I., S.I., P.O. 5-Bit S.R. 70 x 140 9800 158 62 24 450
SN1286 P. L. Serial 5- Bit ring counter 70 x 140 9800 169 58 30 327
SN1287 Dual P. L. Count to Zero 5-Bit
R.C. 70 x 110 7700 153 50 33 230
SN1288 Dual P. L. S. S., 5-Bit R. C. 70 x 140 9800 191 51 30 327
SN5484 Active Element Memory (AEM) 60 x 120 7200 100 72
I
40 180SN5495 4-Bit UP/OOWN Shift Reg. 70 x 120 8400 156 54 33 255
SN5497 Synchronous BCD decade counter 75 x 120 9000 171 53 28 320
TOTAL 111,950 1982
-
401-Average 7000 124 56 25 280
Current Status of Large Scale Integration Technology 69 Considerable improvement is attained in. the
effi-ciency of the circuit technology for IECs compared to ICs. One aspect of this can be understood with ref-erence to Figure 4. The basic Series 54 I C gate is shown at the top left of the figure, while variations of this gate used in the Series 54 IECs are shown in the other three parts of the figure. For example, the in-ternal/expander gate allows for wired-ORing on the chip. Also, since it is used only on the chip, it does not need the high driving capability required when coming off the chip, and requires only 3 devices com-pared with 9 for the basic Series 54 gate. For the latter, the totem-pole output is used in order to drive capaci-tive loads. The IC gate must be designed with many of these factors in mind and of necessity involves com-promises.
Vee Vee
la) SERIES 54le GATE Ib) INPUT GATE
Vee Vee
~
Ie) INTERNAUEXPANDER GATE Id) OUTPUT GATE
Figure 4-Circuits used in Series 54 T2L ICs and IECs
We can summarize at this point by stating that the semiconductor industry has moved to higher levels of integration by the combined effect of employing high resolution technology so that less area is required for a device, and by utilizing chips of larger area.
To what degree can we expect to increase the com-plexity levels attainable on chips, while at the same time gain in over-all savings? This question has been studied at Texas Instruments during the past year.
Similar studies have been reported by Fairchild7 and RCA3 and no doubt are being carried on through-out the industry. Because of the proprietary nature of process-yield information, we are not at liberty to reveal the detailed information of the study; however, we can report certain information that will be of in-terest.
B. Yield versus area
The study was conducted using Series 54 pro-duction data. Two particular goals were emphasized:
(1) the establishment of the dependence of yield on chip area, and (2) the establishment of the major yield loss mechanisms. Item 1 would allow for pro-jection of chip areas into the future, based on to-day's technology, while item 2 provides a basis for improving over-all yield. This latter subject goes beyond the scope of this paper, so will not be dis-cussed further.
FLOW CHART FO~ DATA COLlICTION SERIES 54 INTEGRATED CIRCUIT
15470, 5472. 7490)
Figure 5 - Flow chart defining yield versus area study (photograph route) and yield loss mechanism study (slice route)
la) Ib) lei
Figure 6 - Masks defining areas for yield versus area study
70 Fall Joint Computer Conference, 1967
Figure 7 - Typical slices in yield versus study - the X's designate faulty units
Figure 5 diagrams the flow chart for data collection and analyses. Photographs of slices after functional probe were studied to determine yield as a function of area. The three products studies were two flip-flops of area 3300 mil2 (5470 and 5472) and one IEC of area 5750. mil2 (5490). In order to study the effect of area on yield, a set of overlay masks was defined as shown in Figure 6. Note that each mask defines an area twice as large as the previous one. By counting the good units within the area defined by the overlay
mask and dividing by the total number of units on the slice, the yield as a function of bar area is attained.
Actual slices are shown in Figure 7.
The data of yield versus area were plotted on semi-log paper. The simple theory of random defects pre-dicts a dependency:
y = B exp (-A Area) Log Y = Log B - A Area
B = non-random yield loss
Y = yield A = average defect density
Current Status of Large Scale Integration Technology 71
100
10
~ 9 LLI 1
>=
0.1
0.01
0 10 20 30
UN ITS OF AREA Figure 8 - Plot of yield versus area (relative)
50
This defines a straight line function on semi-log paper as shown in Figure 8. The actual data followed a line of the general shape shown by the data line of the figure. Because of proprietary considerations, the abscissa of Figure 8 is relative - not actual area. The important conclusion established by this study is that yield holds up for larger areas than simple theory predicts. In a qualitative sense we interpret that good units tend to cluster, and, likewise, defects tend to cluster, Examples in Figure 7 show this quite graphi-cally; there are relatively large areas free of defects, and areas where defects cluster. This is particularly so around the slice periphery.
This study of yield versus area has led us to the con-clusion that the LSI chip technology has by no means exhausted itself at the areas of 10,000 miI2 represented in Table III. Using the data obtained in this study, along with some reasonable forecasting of yield im-provement that will take place during the next few years, we forecast that chip technology will be useful for areas as large as ~ in. x ~ in. = 62,500 mil2.
The other major factor that governs complexity level on a chip is the area required for a device.
We have seen over the past five years significant im-provements in optical technology and we forecast that improvements will continue to be made. For further discussion of optical factors the reader is referred to the discussion of Figure 21 in Ref. 6.
The combined effect of improved yield such that larger chip areas will be useful, along with the smaller areas required for circuits, leads us to forecast the following PL complexity levels for the 1970's:
Logic: 250 gates/chip Memory: 500 bits/chip
Texas Instruments has a program to reach these complexity levels by an extension of the Series 54
technology to chip sizes of 62,500 mil2, retaining to-day's device geometries. Thus we have:
Chip size - 62,500 mil2
Logic - 250 mil2/gat~250 gates/chip Memory - 125 mil2/gat~500 bits/chip
New designs which are geared for production in the 1970's should consider· these complexity levels as attainable goals. The actual way the complexity level is achieved may differ somewhat from the above figures, e.g., smaller device geometries could be used resulting in smaller chips.
Figure 9 - Family of plug-in IC and IEC packages
In summary, yield has improved to where, in 1967, IECs of 10,000 mil2 containing 35-40 T2L logic cir-cuits are now in or near production. Designs aimed for production in the seventies should comprehend chips containing up to 250 logic gates or 500 memory bits. Packages are under development as shown in Figure 9 with up to 50 pins per package to accom-modate these chips.
C. Custom products versus standard products The question of custom products versus standard products is not a new one to the semiconductor in-dustry. At the device level many custom transistors are manufactured exclusively for a single customer.
Integrated circuits in their early phases attempted to solve the custom-product problem by a master slice with mixtures of transistors, diodes, and resis-tors which could be interconnected by specific metal-ization patterns to provide a specific circuit for a customer. While the master slice has proved effective for varying a basic circuit, it has not been used for a broad range of circuits. Instead, the problem of
cus-72 Fall Joint Computer Conference, 1967
tom versus standard products has been handled differently. Custom lines have been designed, de-veloped, and placed into production for large custom-ers whose total business warranted the expense of this approach. Often these custom developments have led to standard product lines patterned after them, and a large part of the industry requirements has been satisfied by standard product lines.
However, we must not conclude that a similar course will necessarily follow for IECs. A useful figure for analysis of the question was recently pub-lished by IBM.B Figure 10 plots the number ofuniqll:e parts versus level of complexity (level of integration) for Central Processing Units (CPUs) of 1 K, 10 K, and 100 K circuits, respectively. We note that for complexity levels of 3-4 ·circuits the number of unique parts is relatively small. This is a key reason for the wide acceptance of standard product integrated cir-cuits.
Complexity levels from 10-250 circuits pose the most difficult part-number problem, since high num-bers of unique parts imply relatively small usage of the corresponding parts.
Figure 10- Plot of number of unique parts versus level of integration
Thus we conclude that an efficient, low-cost, quick-turnaround method will be needed to supply custom IECs in the complexity range of 10-250 circuits.
There are many different approaches - but all appear to focus on three basic premises: the first is that a good computer-aided design capability be established so that low-cost masks can be designed in a short time.
Secondly, automatic artwork generation and mask making are required. Finally, some form of master-slice technology is needed to lessen the .processing expense and to shorten the turnaround time.
Fairchild has described a master-slice approach for bipolar (DTL) technology. Master chips of 8800 mil2, containing 32 three-input NAND gates, have.
been defined. One can expect these chip areas to increase in size to allow for greater complexity levels.
RCA has chosen ECL as its basic approach for
Texas Instruments has defined a master-slice approach as a companion approach to the standard IC and IEC Series 54 chip technology. Table IV summarizes this program. Since this program is rep-resentative of the custom-wired LSI chip-technology programs which industry is developing, we shall detail some of its aspects.
The three approaches outlined above, Fairchild-DTL, RCA-ECL, and TI-T2L, while varying in de-tail, have all taken the same basic approach; namely, a master slice which has all diffusions made as the standard item. Personality or customization is im-parted through first- and second-level metalization.
The three approaches outlined above, Fairchild-DTL, RCA-ECL, and TI-T2L, while varying in de-tail, have all taken the same basic approach; namely, a master slice which has all diffusions made as the standard item. Personality or customization is im-parted through first- and second-level metalization.