Each CPU contains an identical, independent computation section. A computation section consists of operating registers and functional units associated with three types of processing: address, scalar, and vector.
Address processing operates on internal control information, such as addresses and indexes, and has two levels of 24-bit registers and two integer arithmetic functional units. Scalar and vector processing are performed on data.
A vector is an ordered set of elements. A vector instruction operates on a series of elements repeating the same function and producing a series of results. Scalar processing starts an instruction, handles one operand or operand pair, then produces a single result.
The main advantage of vector over scalar processing is eliminating instruction start-up time for all but the first operand. Scalar processing has two levels of 64-bit scalar registers, four functional units dedicated solely to scalar processing, and three floating-point functional units shared with vector operations. Vector processing has a set of 64~element registers of 64 bits each, five functional units
dedicated solely to vector applications, and three floating-point functional units supporting both scalar and vector operations.
Address information flows from Central Memory or from control registers to address registers. Information in the address registers is
distributed to various parts of the control network for use in controlling the scalar, vector, and I/O operations. The address
registers can also supply operands to two integer functional units. The units generate address and index information and return the result to the address registers. Address information can also be transmitted to
Central Memory from the address registers.
Data flow in a computation section is from Central Memory to registers and from registers to functional units. Results flow from functional units to registers and from registers to Central Memory or back to functional units. Data flows along either the scalar or vector path, depending on the processing mode. An exception is that scalar registers can provide one required operand for vector operations performed in the vector functional units.
The computation section performs integer or floating-point arithmetic operations. Integer arithmetic is performed in twos complement mode.
Floating-point quantities have signed magnitude representation.
Floating-point instructions provide for addition, subtraction, multiplication, and reciprocal approximation. The reciprocal
approximation instructions provide for a floating-point divide operation using a multiple instruction sequence. These instructions produce 54-bit results (I-bit sign, IS-bit exponent, and 48-bit normalized coefficient).
Integer or fixed-point operations are integer addition, integer subtraction, and integer multiplication. Integer addition and subtraction operations produce either 24-bit or 54-bit results. An integer multiply operation produces a 24-bit result. A 54-bit integer multiply operation is done through a software algorithm using the
floating-point multiply functional unit to generate multiple partial products. These partial products are then shifted and merged to form the full 54-bit product. No integer divide instruction is provided; the operation is accomplished through a software algorithm using
floating-point hardware.
The instruction set includes Boolean operations for OR, AND, equivalence, and exclusive OR and for a mask-controlled merge operation. Shift
operations allow the manipulation of either 54-bit or I28-bit operands to produce 54-bit results. With the exception of 24-bit integer arithmetic, most operations are implemented in vector and scalar instructions. The
integer product is a scalar instruction designed for index calculation.
Full indexing capability allows the programmer to index throughout memory in either scalar or vector modes. The index can be positive or negative
Characteristics of a CPU computation section are summarized as follows.
• Integer and floating-point arithmetic
• Twos complement integer arithmetic
• Signed magnitude floating-point arithmetic
• Address, scalar, and vector processing modes
• Fourteen functional units
• Eight 24-bit address (A) registers
• Sixty-four 24-bit intermediate address (B) registers
• Eight 54-bit scalar (S) registers
• Sixty-four 54-bit intermediate scalar (T) registers
• Eight 54-element vector (V) registers, 54 bits per element
OPERATING REGISTERS
Operating registers, a primary programmable resource of a CPU, enhance the speed of the system by satisfying heavy demands for data made by the functional units. A single functional unit can require one to three operands per clock period (CP) to perform the necessary functions and can deliver results at a rate of one per CP. Multiple functional units can be used concurrently.
A CPU has three primary and two intermediate sets of registers. The primary sets of registers are address, scalar, and vector, designated as A, S, and V, respectively. These registers are considered primary
because functional units can access them directly.
For the A and S registers, an intermediate level of registers exists which is not accessible to the functional units but acts as a buffer for the primary registers. Block transfers are possible between these
registers and Central Memory so that the number of memory reference instructions required for scalar and address operands is greatly reduced. The intermediate registers that support the A registers are referred to as B registers. The intermediate registers that support S registers are referred to as T registers.
ADDRESS REGISTERS
Figure 4-1 shows registers and functional units used for address processing. The two types of address registers are designated A
registers and B registers and are described in the following paragraphs.
A REGISTERS
Eight 24-bit A registers serve a variety of applications but are
primarily used as address registers for memory references and as index registers. They provide values for shift counts, loop control, and
channel I/O operations and receive values of population count and leading zeros count. In address applications, A registers index the base address for scalar memory references and provide both a base address and an
address increment for vector memory references.
The address functional units support address and index generation by performing 24-bit integer arithmetic on operands obtained from A registers and by delivering the results to A registers.
Ai
Exchange contro I
Vec tor
control Sj Si Pop/LZ
Shifts
Multiply Add
/---"----+----+-+--+--+---4 .. Address /---...--.-..+--+-.-+--~ .. funct iondl
L-L/fIf---+-..---+--+-+---I uni ts
Ai Ak
Figure 4-1. Address Registers and Functional Units
Data is moved directly between Central Memory and A registers or is placed in B registers. Placing data in B registers allows buffering of the data between A registers and Central Memory. Data can also be transferred between A and S registers and between A and Shared Address (SB) registers.
The Vector Length (VL) register and Exchange Address (XA) register are set by transmitting a value to them from an A register. The VL register can also be transmitted to an A register. (The VL register is described under Vector Control Registers later in this section.)
When an instruction delivering new data to an A register issues, a in the following instructions:
Octal Code CAL Syntax