Connector Descriptions

Connector Descriptions

Two connectors, P1 and P2, connect the VMIVME-3113A Board to the VMEbus backplane. The connectors are 96-pin DIN type. The primary connector, P1, contains the address data and control lines and all additional signals necessary to control data transfer and other bus functions. The VMIVME-3113A Board uses four of the user I/O pins of connector P2 to allow an external trigger input and a status output. The P2 connector pin and signal assignments are shown in Figure 2 on page 52 and Table 2-8 on page 53.

The P3 and P4 connectors are 96-pin male DIN connectors. Their primary source is Panduit, PN 100-096-033. A compatible connector is AMP 925486-1 with AMP 530151-6 crimp pins. These connectors support the 32 single-ended or 32 differential analog inputs each with an associated analog ground pin. For P3 connector pin and signal assignments, refer to Figure 2-3 on page 54 and Table 2-9 on page 55. For P4 connector pin and signal assignments, refer to Figure 2-4 on page 56 and Table 2-10 on page 57.

The P3 and P4 connectors have an "A" row (A1 through A32), a "B" row (B1 through B32) and a "C" row (C1 through C32). All "A" row pins are the high side of the input signal. All "C" row pins are the low side of the input signal. The preferred method of connecting analog input signals is to connect both high and low inputs for each channel (differential). Differential inputs provide for very high common-mode noise rejection by rejecting differences in ground potential between the analog transmitter and the VMIVME-3113A Board. The board is factory configured to accept differential inputs.

All "B" row pins are connected to the internal analog ground, and are available to the system if 96-wire cables with 0.033-inch spacing are used for the P3 and P4

connections.

A second method of connecting analog inputs is referred to as "pseudo-differential".

In this connection scheme, only one ground reference is brought to the board and connected to the P4 connector at pin C1. This implies that all connected channels from the field must be referenced to the same ground. This method has some of the advantages of differential inputs in that it rejects ground differences, but is not as effective in common-mode noise rejection. Jumper J2 must be installed to enable this mode. In addition, the SIP resistors on the inputs must be in the single-ended position as described in "Differential or Single-Ended Operation" on page 45.

A third method of connecting analog inputs is as "single-ended" inputs. This method uses the on-board analog ground as the input signal reference. This is generally the least accurate of the three methods. However, in a low-noise environment and when short cabling is used, this method will work well. The input SIP resistors must be moved from the differential to single-ended sockets (refer to "Differential or Single-Ended Operation" on page 45.) and jumper J1 must be installed.

A Connector and I/O Cable Application Guide (Document No. 825-000000-006) is available from VMIC that provides additional information concerning the field connections, the use of round cables and a thorough explanation of compatible connectors and cabling techniques.

2

Figure 2-2 P2 Connector Pin Configuration

ROW

Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 Pin 16 Pin 17 Pin 18 Pin 19 Pin 20 Pin 21 Pin 22 Pin 23 Pin 24 Pin 25 Pin 26 Pin 27 Pin 28 Pin 29 Pin 30 Pin 31

REAR VIEW OF BOARD A

C B

Connector Descriptions

2

Table 2-8 P2 Connector Signal Assignments

Pin Row C Row B Row A

2

Figure 2-3 P3 Connector Pin Configuration ROW

Pin 32 Pin 31 Pin 30 Pin 29 Pin 28 Pin 27 Pin 26 Pin 25 Pin 24 Pin 23 Pin 22 Pin 21 Pin 20 Pin 19 Pin 18 Pin 17 Pin 16 Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3

FRONT VIEW OF CONNECTOR C

PC BOARD A

B

Connector Descriptions

2

Table 2-9 P3 Connector (Front Panel Inputs) Signal Assignments

Pin Row A Row B Row C

2

Figure 2-4 P4 Connector Pin Configuration ROW

Pin 32 Pin 31 Pin 30 Pin 29 Pin 28 Pin 27 Pin 26 Pin 25 Pin 24 Pin 23 Pin 22 Pin 21 Pin 20 Pin 19 Pin 18 Pin 17 Pin 16 Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3

FRONT VIEW OF CONNECTOR C

PC BOARD A

B

Connector Descriptions

2

* For pseudo-differential input, P4-C1 is the low-side (GND) reference for all input channels. Refer to "Connector Descriptions" on page 51 for pseudo-differential input description.

Table 2-10 P4 Connector (Front Panel Inputs) Signal Assignments

Pin Row A Row B Row C

2

CHAPTER

Programming

Contents

Control and Status Register Descriptions . . . 60 Initialization By Reset . . . 64 Controlling and Reading the Analog-to-Digital Converter Data . . . 65 Changing A/D Operating Modes . . . 71 Program Example . . . 72

Introduction

Communication with the VMIVME-3113A takes place through 128 contiguous, 16-bit register locations which are mapped into the VME short I/O address space. Most VMEbus CPUs access the short I/O space as if it were a 64-Kbyte block of

conventional memory. Consult your CPU manual to determine the address of this block.

The VMIVME-3113A supports byte and word (16-bit) accesses. The order of the bytes within a word depends on the model of CPU used. For instance, most 68000-based CPUs put the most significant byte at the same address as the word. The least

significant byte is at the next address. When registers are described as words here, this byte order is used. Note that if the AUTOSCAN data is read in two separate byte reads, they may be from different conversion cycles. This can introduce a large error in the reading.

Functions of the communications registers, which are discussed in detail within this section, are summarized in Table 3-1 on page 60. Some of the registers are not used, and are labeled "reserved". Reserved registers may be duplicate mappings of normal Control Registers. They should not be used, since they could be affected by a design change. Location 0 (word) simply reads the constant 11xx HEX. This is the board ID.

3

3