t Only usable with the H-822-3, 900-line-per-minute printer
SYSTEM CONFIGURATION
§ 03!.
.4 lO-TAPE PAIRED LARGE BUSINESS-ORIENTED SYSTEM (CONFIGURATION VII B, Contd.) Deviations from Standard Configurations:
Rental: .
card reading faster by 60%.
card punching faster by 15%.
printing faster by 80%.
$5,950.
Equipment
H-804-3 Economy Tape Unit 30,000 char/sec.
H-817 Auxiliary Control
H-811-6 Control Unit
H-827 Card Read/Punch 800 cards/min reading 250 cards/min punching
.H-822-3 High Speed Printer 900 lines/min.
Total:
502:031.401
Rental
$ 550
950
1;950
550
1,950
$ 5,950
SYSTEM CONFIGURATION
§ 031.
.5 20-TAPE INTEGRATED LARGE BUSINESS-ORIENTED SYSTEM (CONFIGURATION VIII A) Deviations from Standard Configuration:
Rental:
On- Line Equipment
.1 additional magnetic tape transfer.
card reading slower by 20%.
printing slower by 10%.
54 additional index registers.
$54, 000 per month.
Equipment
502:031.500
Basic Storage of 24, 576 words and 256-word Control
Memory $ 8,000
Optional Features Ip.cluded:
Central Computer and Console.
Floating Point Option
Model H-807-3 Controller Card Reader
Model H-827 800 cards/min Card Punch
Model H-827 250 cards/min High Speed Printer
Model H-822 900 lines/min
Model H-806-3 Controller
3 Magnetic Tape Controllers Model H-803 with
20 H-804-4 Tape Units
(133,000 alphameric char/sec.) each.
Total:
. . • • . . • • • . . • • • Floating Point Option.
20,480 words of store.
8,550 2, 100
1,100
550
1,950 1,450
30,300
$ 54,000
502:031.600
§ 03!.
.6 PAIRED 20-TAPE GENERAL SYSTEM (CONFIGURATION VlIIB) On- Line Equipment
Deviations from Standard Configuration:
Rental.
HONEYWELL
800
tape unit 10% faster.
faster card reading (300 instead of 100 cards/min).
54 additional index registers.
$39, 125 per month.
Equipment Basic Storage of
4,096 words and 256-word Control Memory, plus 3 additional storage units, each of 4, 096 words.
Cenu-al Computer and Console.
Including Floating Point Option.
Card Reader
Model H-823: 240 cards/
min with
Controller H-807-1
2 Magnetic Tape Controllers Model H-803-4 with 8 H-804-4 Tape Units (133,000 alphameric char/sec) each.
Total:
Rental
$
4,8008,550 2,100
125 950
8,200 14,400
Total including 00- Line Equipment:
$
39,125$
46,925 Optional Features Included: . . . . . Floating Point Option.12, 288 words of storage.
2/63
SYSTEM CONFIGURATION
§ 031.
.6 PAIRED 20-TAPE GENERAL SYSTEM (CONFIGURATION VIlIB, Contd.) Off- Line Equipment
Deviations from Standard Configuration:
Rental: •
o
card reading slower by 20%.
printing slower by 10%.
$7,800.
Equipment
H-804-3 Economy Tape Unit 32, 000 chari sec
H-817 Auxiliary Control
H-811-4 Control Unit
H-827 Card Read/Punch Unit 800 cards/min Reading 250 cards/min Punching
H-804-3 Economy Tape Unit 32, 000 char/sec
H-818 Off Line Printer Control
H-822-3 High Speed Printer 900 lines/min
Total
502:031.601
Rental
$ 550
950
1,700
550
$ 3,750
$ 550
1,550
1,950
$4,050
$ 7,800
502:041.1 00 Honeywell 800 Internal Storage Control Memory INTERNAL STORAGE: CONTROL MEMORY
§ 041
.1 GENERAL . 11 Identity:
.12 Basic Use:
. 13 Description
Control Memory .
to hold 8 standard sets of data for programs and for independent pairs of I/O channels.
The function of the Control Memory is to control each of a number of programs. For this reason, it is divided into eight segments, each of which con-tains sufficient controls and auxiliaries for a single program. The contents of a single segment, listed below, include 8 index registers and 12 or 16 gen-eral purpose registers, in addition to sequence, in-terrupt, and masking facilities.
Each separate register can hold a 16-bit word, and basically contains one address. The first two reg-isters contain counters for handling multiword op-erations, one for the source and one for the destina-tion. The others control various features of the operation.
Table of Special Register Names, Subaddresses, and Mnemonic Address:
Sub- Mnemonic
Name address Address
00 AU! Arithmetic Control Counter No.1
01 AU2 Arithmetic Control Counter No.2
02 SC Sequence Counter 03 CSC Cosequence Counter 04 SH Sequence History Register 05 CSH Cosequence History Register 06 UTR Unprogrammed Transfer
Register
07 MXR Mask Index Register 08-15 XO-S7 Index Registers
16-23 RO-R7 General Purpose Registers 24-27 SO-S3 General Purpose Registers 28 RAC* Read Address Counter 29 DRAC* Distributed Read Address
Counter
30 WAC * Write Address Counter 31 DWAC* Distributed Write Address
Counter
* In those special register groups not associated with active input and/or output channels, RAC.
DRAC, and/or WAG, and DWAC are replaced by
13 Description (Contd.)
Registers No. 03 through 06 are used for sequence control purposes, and provide for three distinct se-quencing arrangements within the same program.
For practical purposes, the Sequence and Co-sequence counters are similar in function, provid-ing two normal program sequence controls between which the programmer can alternate as he chooses.
This provision allows reduction in program length of some 5 to 10 per cent, depending on programming philosophy .
The third sequencing arrangement is the Interrupt system (described in Paragraph .333 of the Cent:J;"al Processor section). In this system, a basic address is stored in the Unprogrammed Transfer Register.
This address is incremented to define both the cause of the interruption and the instruction which was in control at the time.
Eight index registers are included in each segment of the Control Memory. These act as base addresses rather than as augmenters. Each index register can contain an address anywhere in storage, but the instruction has only eight bits (Le., up to 256) to specify the increment or decment to be applied. This limitation considerably re-stricts the utility of the index registers; however, indirect addressing is also available (see Central Processor, Paragraph .238).
Because the cycling of the Control Memory is offset by half a cycle from the cycling of the Main Memory, no easy rule is available to show the cost of index-ing. The rules for each case of each instruction are spelled out in an Appendix to the Programmers Ref-erence Manual. To illustrate the complexity in-volved in detailed timing a typical entry from this appendix follows.
Basic
Time in Modification of Instruction Memory Basic Time
Cycles
TS (cont) 1 mc if C is direct
special register or indirect memory location address 1 mc if C is indexed
502:041.130
§ 041. .13
.13 Description (Contd.)
2/63
Six special registers are used to control the two in-put and outin-put channels which may have been con-nected to each sector. Two control the actual trans-fer to and from the I/O device, while two control the storage areas being used if the transfers are to be scattered around the store. This latter practice,
HONEYWELL 800
Description (Contd.)
which doubles the I/O demands on the store, and may introduce a considerable number of I/O restric-tions, is not often followed.
M~my instructions are available to provide for mask-ing of the operands. The Maskmask-ing Control Register contains the address, anywhere in storage, qf the mask to be used. This mask is used on all the op-erands in a masked operation.
• STANDARD
E D P
• REPORTS
502:042.100 Honeywell 800 Internal Storage Core Storage INTERNAL STORAGE: CORE STORAGE
§ 042.
Additional H-802 Modules.
working storage.
The core storage is used as the main computer storage. It is accessed independently, and without lockouts, by each program running in parallel.
Some instructions allow for masking of each of the operands. Irrespective of whether one, two, or three operands are referred to by the instruction, the same mask is applied to each. The basic ma-chine has a core storage of 4, 096 words, each con-sisting of 48 data bits and 6 check bits. Six mod-ules, each of 4,096 words, can be connected.
First Delivery:
. .
1960 .Reserved Storage: . none.
Purpose Number of locations
Index registers: none.
Arith registers: none.
Logic registers:. none.
I/O control:
. .
none •PHYSICAL FORM
Storage Medium: . magnetic core.
Storage Phenomenon: direction of magnetization.
Recording Permanence Data erasable by
instruction:. . . yes.
Data regenerated
constantly: . . . yes.
Data volatile:
. .
yes .Data permanent: . no.
Storage changeable: no.
Access Techniques
Recording method: . coincident current.
Type of access:
..
all locations available each 6 microsecond cycle.• 29 Potential Transfer Rates .292 Peak data rates
Cycling rates: 133,000 cps.
1 word.
.3 .31
Unit of data: . Conversion factor: . Gain factor:
DATA CAPACITY Module and S~stem Sizes
Minimum H-802 Maximum Storage Module Storage
Words: 4,096 4,096 28,672
Characters: 32,768 32,768 219,376 Instructions: 4,096 4,096 28,672
• 32 Rules for Combining
any 1 word each 6-micro-second cycle.
STORAGE: . . . none.
.8 ERRORS, CHECKS AND ACTION Check or
Error Interlock Action
Invalid addre.s: check sequence interrupt.
Receipt of data: check of 6 sequence interrupt.
bits/word
Recording of data: generation of sequence interrupt.
6 bits/word
Recovery of data: check of 6 sequence interrupt.
bits/word
Dispatch of data: generation of sequence interrupt.
6 bits/word
Timing conflicts: check if any sequence interrupt.
data lost Physical record missing: not possible.
Reference to locked area: not possible.
Circuit failure: check halt.
Input area overflow check sequence interrupt after next word
overwritte~ .•
.STAI<OARO
•
E D P
REPORTS
502:043.100 Honeywell 800
Internal Storage
H-860 Magnetic Disc File INTERNAL STORAGE: MAGNETIC DISC FILE
§ 043 .
. 1 GENERAL
• 11 Identity:
• 12 Basic Use:
· 13 Description
Magnetic Disc file.
Bryant Series 4000.
H-860.
auxiliary storage •
This unit consists of a controller plus one or more cabinets of discs. A maximum number of eight disc cabinets can be connected, providing a capacity of from 50 to 805 million alphameric characters.
Access to the disc is achieved by addressing data records, each of 512 alphameric or 768 numeric characters, arranged into 64 words. Any record in a track can be addressed independently.
Slightly less than 1 percent of the file (that part over which the heads are positioned) is available within 41 milliseconds, assuming average latency for disc rotation and a constant of 6 milliseconds for data transfer.
To gain access to another track involves waiting the 41 milliseconds for access plus an additional 60 to 130 milliseconds for lateral head movement. Thus, an average access, including head position changes, takes 136 milliseconds, allowing nearly 480 records per minute to be obtained or stored.
As each disc unit of 100 million alphameric charac-ter capacity can position its heads independently of the other units, time-sharing is possible with more than one disc unit, and can result in rates of up to 1200 64-character records per minute.
Full specifications for the unit are still to be announced.
.14 • Availability: .
· 15 First Delivery:
.16 Reserved Storage:.
· 2 PHYSICAL FORM . 21 Storage Medium:
· 22 Physical Dimensions
· 222 Drum or Disc Diameter:
Thickness: .
9 months.
attached to other computers'?
attachedtoH-800, 1963.
none.
magnetic disc.
39 inches.
thin.
.23 Storage phenomenon: direction of magnetization.
.24 Recording: Permanence .241 Data erasable by
instructions: yes.
.242 Data regenerated
constantly: no.
.243 Data volatile: no .
· 27 Interleaving Levels:
· 28 Access Techniques
· 281 Recording method:
· 283 Type of access Description of stage
Move head to selected band:
Wait until record is in position:
Transfer of
Possible starting stage yes.
yes, if a record on the same band of any disc face was previously selected.
no, but previous stage time may be zero.
· 29 Potential Transfer Rates
· 291 Peak bit rates Cycling rates:
Bits/inch/track:
Compound bit rate:.
.292 Peak data rates Cycling rates:
Unit of data:
Conversion factor: . Gain factor: . Loss factor:
Data rate:
Compound data rate:
900 rpm.
variable.
615,000 bits/ sec.
variable .
502:043.300
§ 043.
.3 DATA CAPACITY .31 Module and System Sizes
Modell Model 2
Minimum System 12 the control unit, each unit must contain 24 Discs. No more than 8 units can be connected at one time.
. 41 Identity:... . Model H- 860 Control Unit . .42 Connection to System
.421 On-Line:
· 44 Data Transfer Control . 441 Size of load: . . . . 442 Input-Output area:
• 445 Synchronization:
· 447 Table control:
. 448 Testable conditions:
· 5 ACCESS TIMING .514 Accessible locations
By single stack With no movement:
With all movement: .
general error and/or busy check.
HONEYWELL 800
.514 Accessible locations (Contd.) By all stacks
.515 Relationship between
stacks 'and locations:. none.
.52 Simultaneous Operations A
searching for a record.
internal computation.
.53 Access Time, Parameters, and Variations
• 532 Variation in access time, in msec.
.6 .7
.71
Stage Variation
Head positioning: ••
a
or 60, 000 to Waiting for the disc tobe in position: • Transfer ·of record:
Total: • • • • •
AUXILIARY STORAGE PERFORMANCE Data Transfer
Pair of storage units possible
With Self: no .
• 73 Effective Transfer Rate
.8
With Main
Memory: not yet determined . this depends on the timing
of the interrecord gap.
ERRORS, CHECKS AND ACTION Error
Invalid address:
invalid code:
Check or Interlock Action
none unpredictable
Dot possible.
::~:!~~nO; :t:'~a: I
Recovery of data:
Dispatch of data:
Timing conflicts:
Physical record missing:
Reference to locked area:
not yet specified.
. S I " " ' "
•
E D P
REPORIS
502:051.100
Honeywell 800
Central Processor
CENTRAL PROCESSOR
§ 05l.
.1 GENERAL
• 11 Identity: . . H-SOl Central Processor.
H-SOlB Central Processor.
.12 Description (Contd.)
part of the orthotronic recovery routine, this instruction is used to locate bad frames after an erroneous "read" operation. Another instruction permits orthotronic control words to be formed and appended to the output records .
. 12 Description:
The H-SOl Central Processor uses three-address.
instructions. Each operand address, which refers to a word in either Control Memory or Main Memory, can be written in a direct, indexed, or indirect manner. Indirectly addressed operands can themselves be indexed.
Input-output on the H-800 is handled in six-bit alphameric code, whereas the arithmetic instruc-tions work in foar-bit numeric requiring pre- and post-arithmetic conversion. No special instructions exist for handling the conversion from . one to an-other; all must be programmed. Editing instruc-tions to allow zero suppression, comma insertion, etc., are not included in the repertoire, and carry-ing out such functions can take over 500 micro-seconds per character, depending on the require-ments and the programmer.
Some inefficiency in storage utilization can occur as a result of the addressing methods used. These methods divide the storage into two parts: one, a maximum of 2, 048 words, which can be directly addressed, and another which "requires special addressing through the control memory. While programs remain small, the inefficiencies are probably low, but as the average installation in-creases its storage size, the inefficiencies increase because a greater number of banks are used by the
The Accumulate instructions repeat themselves n times, adding each time into the accumulator.
These instructions permit a number of different operands to be accumulated by one instruction, although signs are not treated arithmeticaJly.
No inter-program protection is automatically avail-able for data, instructions, sequence registers, etc.
It is left to individual installations to ensure that time-sharing programs do not interfere with each other.
Instructions can treat data as words, items, or records for the purpose of transferring them into, out of, or within memory. An item is a group of words followed by an "end-of-item" word; a record is a group of words or items followed by an end-of-record word. Each time an end-of-item word is encountered during a transfer, an automatic table look-up operation locates the position in memory which the new item is to occupy.
Interruption can be caused by any of a number of conditions and results in a forced transfer of con-trol. The destination (which is set up relative to a programmer-controlled address) distinguishes seven cases: Parity, Beginning or End of Tape, Input-Output error, Add/Subtract error, Division error, Exponential underflow, Exponential overflow.
program(s) running at anyone time. .14 First Delivery: 1960.
Indexing is performed by adding an increment from the instruction to one of the 64 index registers.
(The increment must be less than 256.) In indirect addressing the instruction can also contain an incre-ment (less than 32) which can be added to the address in Main Memory after the instruction is performed, thereby automatically allowing the addresses in a loop to be modified.
Arithmetic is performed on complete words, in either binary or decimal mode. Partial words can be used as operands for some instructions through use of a mask word which is applied to each of the operands in the instruction in turn. The basic machine has facilities for fixed point addition, sub-traction, and multiplication, but not division; it has no facilities for floating point operations. The H-SOl B has facilities for all fixed and floating point operations.
An instruction which checks each of six parity bits associated with a 4S-bit data word is available. As
.2 PROCESSING FACIUTIES
• 21 Operations and Operands
Operation and Variation
• 211 Fixed point digilll in processor register)
"automatic
"indirect (extra digilll in processor register)
. 502:051.212 HQNEYWELL 800
§ 051. .218 Table look-up: none .
. 212 Floating point (available both with and without normalization.)
. 21~ Others
Accumulate: . automatic.
. 213
.214
.215 . 216 . 217
Add-Subtract: "'automatic binary or decimal 40&7.
Multiply: ·automatic
Divide: "'automatic
binary or
AND: automatic}
Inclusive OR: automatic Exclusi ve OR: automatic Comparison
Numbers: automatic.
Absolute: automatic.
Letters: automatic.
Mixed: none.
Code translation: . none.
Radix conversion: none . Edit format
Alter size: • none.
Suppress zero: none.
Round off: none.
Insert point: none.
Insert spaces: non~.
Insert special
character: none.
Float
$:
none.Protection: none.
.221 Negative numbers: . •
binary.
.222 Zero:
.23 Instruction Formats
·.231 Instruction structure:
.232 Instruction layout:. .
in fixed point represen"
tation, the sign is storea as 4 bits, but used .as 1 bit; in floating point, 1-bit sign representation is used.
positive or negative ·zero possible. These behave differently in alphabetic comparisons .
I-word, 3-address instruc-tions.
Typical areas are shown below.
BITS 1