4.5. CONCLUSION 87
88 CHAPTER 4. ROBUSTNESS CHECKING
Chapter 5
Outlook
While both contributed approaches are finished and can be used to solve the corresponding problems, expansions to increase the performance or widen the field of application are still possible.
A comparison between neighboring abstraction levels could provide further possibilities of application. An equivalence check between ESL and a HDL would allow further use of the equivalence checker as it could support the development of hardware systems further along the development cycle. However, both levels are quite different. While an execution on ESL coalues. Thus, the correspondence mapping that defines which initial states and which methods correspond to each other needs to be expanded. While defining corresponding initial states should be straightforward, as we just need to define thnsists of the execution of multiple methods, a system described in a HDL changes its state and outputs during each clock cycle according to its current state and input ve initial assignment of the registers in HDL, the function mapping needs to consider a number of methods on ESL and specific input values over a certain number of clock cycles for the HDL.
Enabling the equivalence check between ESL and HDL would also allow the use of the equivalence checker together with the robustness checker. In this scenario, a hardened iteration of the system at HDL can be checked for correctness by comparing it to the golden model at ESL. In a next step, tools can deduce the logical circuit from the HDL level and our robustness checker can check that circuit for robustness. If the equivalence check and the robustness check are successful, we have shown that the system at HDL is both correct and robust.
89
90 CHAPTER 5. OUTLOOK
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