the space charge region to ZnO and lead to the observed increase in the capacitance in Fig. 5.21b.
It was found, that the concentration of Na at the hetero-interface can be reduced by depositing a thin layer of Mo prior to the NaF PDT. The Mo layer is supposed to reduce the diffusion rate of Na into the CIGSe, which leads to the beneficial depth profile, with a low Na concentration at the hetero-interface while remaining a high Na concentration in the bulk (Fig. 5.22 with Fig. 5.23). This leads indeed to the best fill factor. Reducing the NaF rate to 1 nm/min was shown to have a very similar effect.
Thus it can be concluded from the correlation of the depth profiles, the C−V curves and the J−V curves, that sodium leads to acceptor states within the GaOx layer, which lifts up the conduction band at the interface and therefore introduces an electron barrier and lowers the extraction of the photo-current.
Potassium was tested as an alternative for sodium. Potassium leads to very good PCEs in substrate devices, where it is supposed, that the potassium atoms sit on Cu sites and are replaced by Cd atoms during the CdS deposition [144]. This leads to a n-type doping of the surface and a reduced interface recombination. This mechanism is unlikely to occur in superstrate devices though, since the deposition sequence is switched, first Zn diffuses into the CIGSe and then K is introduced. And indeed, the use of potassium as a precursor or supplied with a PDT, both lead to similar results as the use of sodium only.
A kink developed in the fourth quadrant, strongly pronounced for the precursor and less pronounced for the PDT. However, the combination of a 5 minute NaF PDT followed by a 5 minute KF PDT lead to a PCE of 11%, compared to 9% for the pure NaF treatment from the same deposition run. A speculative explanation could be, that K atoms replace Cu atoms close to the hetero-interface, which increase the band gap and reduce the interface recombination as observed in substrate devices [145]. In other deposition runs an efficiency of 11% were also achieved for pure NaF treatments. Thus, the KF treatment appears to be beneficial, but this is not yet sufficiently reproduced and secured.
In summary, The NaF and KF PDT lead to a strong increase in efficiency due an increased bulk p-type doping and a reduced bulk recombination rate. Both effects pre-sumably originate from the reduction of ZnCu and InCu states by NaCu or KCu. On the other hand, the efficiency can be reduced by the alkalis if their concentration at the hetero-interface is too high. They are argued to induce NaGa or KGa acceptor states within the GaOx which leads to an electron barrier and a reduced fill factor.
5.3 Comparison with buffer free ZnO/CIGSe
(a) (b)
Figure 5.25: a) J−V curves and b) C−V curve of substrate devices with CdS or i-ZnO buffer. The i-ZnO was deposited via ALD at different deposition temperatures.
reported efficiencies around 12 % [146] [147]. The influence of the substrate temperature during the i-ZnO deposition onto the CIGSe is studied here. The i-ZnO is deposited via ALD and sputtering, the AZO window layer has been sputtered identically for all devices.
Fig. 5.25a shows the J −V curves of substrate devices with i-ZnO buffer layers and one CdS reference device under illumination. The CIGSe absorber were deposited with a standard three-stage process at 560 and a resulting Cu/(Ga+In) ratio of 0.85 and Ga(Ga+In) ratio of 0.3. The CdS reference device exhibits the highest PCE of 14.2 %.
The ALD deposited i-ZnO at 120leads to the second most efficient device, but the FF is considerably lower compared to the CdS device. If the deposition temperature is increased to 210, the VOC starts decreasing from 590 mV to 410 mV. The same result, with only slightly lowerVOC, was obtained from an i-ZnO layer sputtered at 180. If the deposition temperature of the ALD i-ZnO is further increased to 300, theVOCand PCE is reduced to zero, indicating very high interface recombination currents. The corresponding C−V curves are shown in Fig. 5.25b for the two devices deposited at 120and 210. The CdS free devices show a strongly increased capacitance at all applied voltage biases compared to the CdS device.
Discussion The data presented here shows that both deposition methods, ALD and sputtering, lead to very similar device characteristics, whereas the deposition temperature has an unexpected drastic influence. The low FF together with the increased capacitance compared to the CdS device indicate that interfacial acceptor states are again responsible for the lower FF, similar as it was found for the superstrate devices (Sec. 5.2.5). It was however, not possible to find a device model which fits both the J−V andC−V curves sufficiently well. This is likely to be caused by the roughp/n-heterojunction in substrate devices compared to superstrate devices, which reduces the straight forward correlation of theC−V and theJ−V curves and cannot be represented by a one dimensional device model any more.
Figure 5.26: PCE andVOC for ZnO/CIGSe devices in substrate and superstrate configura-tion displayed versus the maximum temperature exposure of the ZnO/CIGSe interface during fabrication. For substrate devices this is the ZnO deposition temperature, for superstrate de-vices the CIGSe deposition temperature. The formation of GaOx in superstrate devices is assumed to lead to the increase of PCE andVOC until it starts limiting the current at 560.
Regarding the nature of the acceptor states, it is argued in [148], that the acceptor states are induced by the VSe-VCu defect complex [48] within the CIGSe. This is unlikely, since it can’t explain the temperature dependence. It could however however be assumed that the acceptor states are induced by copper and sodium diffusion into the ZnO layer or by OSe states at the CIGSe/ZnO interface. It should be noted that the very same trend was observed in Cu2O/ZnO devices [149], which supports the assumption of Cu being responsible for the acceptor states within ZnO. This interpretation would lead to a conclusive model for the CIGSe/ZnO interface, in which the quality of the p/n junction mainly depends on the temperature load that it experiences during fabrication.
The dependence of the power conversion efficiency on the temperature exposure of the ZnO/CIGSe interface is shown in Fig. 5.26 for both configurations, substrate and superstrate. ηandVOCappear to be correlated with the deposition temperature. It seems a plausible assumption, that the acceptor type defect density from diffusion of copper and sodium, increases with increasing temperature. The resulting increased interface defect density reducesηandVOCdue to interface recombination, until, at a certain temperature, a thin layer of GaOx forms at the interface. The GaOx layer reduces the electron density at the interface which reduces the interface recombination, leading again to an increase ofη for increasing temperature. At a certain temperature the Cu diffusion into the GaOx occurs, which again increases the acceptor density at the interface and decreases the electron collection and with it also η.
In summary, it is proposed that the diffusion of Cu and/or Na into ZnO or GaOx is a general problem independent of the device configuration. The acceptor states induced by Cu/Na reduce electron collection and increase interface recombination.