Table D.1:Mapping of AMC ports between the four AMC bays on the CNCB v3.3.
Target bay-port
Source port Source bay 1 Source bay 2 Source bay 3 Source bay 4
6 4-12 1-12 2-12 3-12
7 4-13 1-13 2-13 3-13
8 4-14 1-14 2-14 3-14
9 3-11 4-11 1-11 2-11
10 3-10 4-10 1-10 2-10
11 3-9 4-9 1-9 2-9
12 2-6 3-6 4-6 1-6
13 2-7 3-7 4-7 1-7
14 2-8 3-8 4-8 1-8
and signals for physical Ethernet, USB, and JTAG connectors. The mapping is shown in figure D.3.
D.2.4 AMC bay interconnection
AMC ports 6 through 14 of the four AMC bays provide interconnections between the cards. Of these, ports 6, 10, and 12 are connected to MGTs on the xFP.
Table D.1 shows the exact mapping.
D.2.5 JTAG and programming
A bitstream can be downloaded to the Switch FPGA and the FPGAs on plugged-in xFPs plugged-in two different ways:
1. with a JTAG programmer connected to the JTAG header on the CNCB or, if used, the RTM; the JTAG chains of all xFPs are concatenated into a single JTAG chain, from which missing boards are automatically decoupled; and 2. automatically upon power-up via the slave-serial daisy chain of the Switch FPGA and all xFPs, from which missing boards are automatically decou-pled.
The second mode requires all present xFPs to be set up in slave-serial mode, as described in section D.1.3. This configuration mode is described in the Virtex-5 configuration user guide [135, p. 40]. All FPGAs then are configuration slaves, and the CPLD on the CNCB is the configuration master: It provides the
D.2. CNCB V3.3 181
4 3 2 1
REV_SEL2 REV_SEL1 REV_SEL0 CPLD_ENABLE
0/off 1/on
Figure D.4:DIP switch controlling the automatic programming by the CPLD on the CNCB. Note that the signal names are swapped on the PCB’s assembly print.
configuration data and controls the configuration clock andPROGRAMsignals of the FPGAs.
The configuration file for the slave-serial mode can be generated from the individual bitstreams for the Switch FPGA and xFP-FPGAs with the following command line:
promgen -b -p bin -u 0 <sw_fpga>.bit \
<xfp_1>.bit <xfp_2>.bit <xfp_3>.bit <xfp_4>.bit -o <combined>.bin At least as many bitstreams must be combined as FPGAs are present in the daisy chain. If fewer FPGAs are present, the configuration succeeds and unused configuration data at the end is discarded.
The combined bitstream must be written to the flash memory, which is con-nected to the FPGA and CPLD on the CNCB. Currently, the only way to do this is by accessing the flash with software running on the PowerPC, for which an EDK project with a PLB interface for the flash memory (xps_mch_emc) is required. The flash can then be accessed as a block device by a Linux sys-tem with the correct drivers. Alternatively, theProgram Flashoption from Xilinx SDK can be used to automatically download and execute a standalone flash-programmer binary on the PowerPC. A possible add-on the the CPLD’s functionality, allowing bitstream writing over IPMI, is under development.
The CPLD initiates the automatic configuration process upon power-up or upon a command sent by the IPMC, but only if theCPLD_ENABLEbit of the CNCB’s DIP switch is active (see figure D.4). The CPLD reads the combined bitstream from a specific offset in the64 MiBflash memory. Currently, this offset is fixed to48 MiB. The system design foresees that the offset is config-urable with the DIP switch’sREV_SELbits, so that a backup bitstream can be loaded in case the default one is overwritten by a non-working version. As the combined bitstream has a size of almost16 MiB, a reasonable offset for the
MGT 106B GT11_X0Y0 MGT 106A GT11_X0Y1 MGT 105B GT11_X0Y2 MGTCLK 105 GT11CLK_X0Y1
MGT 105A GT11_X0Y3 MGT 103B GT11_X0Y4 MGT 103A GT11_X0Y5 MGT 102B GT11_X0Y6 MGT 102A GT11_X0Y7
MGT 109B GT11_X1Y0 MGT 109A GT11_X1Y1 MGT 110B GT11_X1Y2 MGTCLK 110 GT11CLK_X1Y1
MGT 110A GT11_X1Y3 MGT 112B GT11_X1Y4 MGT 112A GT11_X1Y5 MGT 113B GT11_X1Y6 MGT 113A GT11_X1Y7
ATCA Fabric Channel 0[7]
ATCA Fabric Channel 0[8]
ATCA Fabric Channel 0[9]
156.25 MHz ATCA Fabric Channel 0[10]
ATCA Fabric Channel 0[11]
ATCA Fabric Channel 0[12]
ATCA Fabric Channel 0[13]
ATCA Fabric Channel 0[14]
ATCA Fabric Channel 0[6]
ATCA Fabric Channel 0[5]
ATCA Fabric Channel 0[4]
156.25 MHz ATCA Fabric Channel 0[3]
ATCA Fabric Channel 0[2]
ATCA Fabric Channel 0[1]
ATCA Update Channel 0(Up) ATCA Fabric Channel 0[15]
Left column Right column
Figure D.5: External connections of the MGTs of the CNCB v3.3, showing transceiver designators, tile locations, and ATCA-channel names. Note that some MGTs have inverted signals for their receiver inputs (marked with ) or their transmitter outputs (marked with ).
backup bitstream would be32 MiB, with the flash’s lower32 MiBreserved for Linux kernels and storage.
D.2.6 Multi-gigabit transceivers
The Virtex-4 FX60 has two columnswith 8 GT11 primitives in each column.
Two neighboring transceivers (designatedAandB) use shared clock resources.
Figure D.5 shows how the transceivers connect to ATCA backplane ports. One clock input of each column is used. In contrast to the Virtex-5 GTX transceivers, there are no limitations on clock-routing distance or required instantiations.
D.2.7 Sensors
The CNCB v3.3 provides the following sensors on the sensor I2C bus accessible from the IPMC:
D.2. CNCB V3.3 183
• A Maxim MAX1239EEE+ 12-channel, 12-bit ADC [136] with slave address 0110101. It measures the following voltages:
– AIN0: VCC1V2 – AIN1: VCC1V8
– AIN2: VCC2V5×3.3/(3.3 + 10) – AIN3: VCC3V3×3.3/(3.3 + 10) – AIN4: VCC5V×3.3/(3.3 + 10) – AIN5:𝑉shunt× 1/(1 + 10)
– AIN6: VCC12V_TOP×1/(1 + 10) – AIN7: VCC12V_AMC1×1/(1 + 10) – AIN8: VCC12V_AMC2×1/(1 + 10) – AIN9: VCC12V_AMC3×1/(1 + 10) – AIN10: VCC12V_AMC4×1/(1 + 10) – AIN11: VCC12V_RTM×1/(1 + 10)
Voltages higher that2 Vare scaled down by voltage dividers to adapt them to the ADC’s dynamic range.
• A Maxim MAX1617AMEE+ temperature sensor [137] with slave address 0011000. It measures its own temperature (located on the PCB near the FPGA) and the FPGA-internal temperature-sensing diode pins.
The voltage𝑉shuntmeasured by the ADC reflects the total power consumed by the CNCB and all plugged-in boards. The voltages used on the CNCB are derived from the48 Vinput of the Zone 1 connector. The48 Vare converted to12 V, from which all other voltages are generated. 𝑉shuntis the voltage dropped over a5 mΩshunt resistor that is put in the12 Vpath before the loads, magnified by a factor of 20 by an Analog Devices AD8210YRZ current monitor [139]. The AD8210 is operated in unidirectional mode with ground-referenced input. The power consumed by the board can be calculated as𝑃 = 12 V × 10𝑉shunt/ 1 Ω.