GENERAL PROCESSOR HARDWARE
CLOCK GENERATOR CYCLES
The clock generator is capable of producing a normal cycle and four variations of the normal cycle used for special functions.
Normal Cycle
The normal cycle consists of two cycles of the high-frequency clock in the high state and two cycles in the low state. For this type of cycle, START H is constantly high, RESET H is low, and elK STOP is low.
The figure shows this cycle.
Clock Stutter Cycle
The clock stutter cycle is generated on all address microcycles and for all internal data transfers among the MOS chips. It is the same as the normal cycle discussed above except that the clock-high time is ex-tended from two cycles of the high-frequency clock to three. This stretched or "stuttered" clock time allows the DAl lines to settle before the address is driven out onto the bus. The cycle also allows extra time for data transfers between MOS chips.
54
Chapter 3-LSI-11 123 Processor
65ClK H
ILI1..JL.JLJLI
MClK H
J
E65 H
---.J
L...-_--'r--L . . - _ . . . J
r
E 130 H
lL-_ _ ...
L-Normal Clock Cycle
The cycle Is generated by the ClK STUT H signal from the bus control PROM being fed through a transparent latch that is enabled during phase time. The output of the latch inhibits the E130 H input to the feedback loop from causing MClK H to go low. Instead, the ring oscillator output drops when E195 H goes high, one cycle of the high-frequency clock later. The stutter cycle is shown in the figure.
65ClKH~
MClK H
J
L...-_---'r--ClK STUT H
L
E130 H
- - _
...E195 H
L
Clock Stutter Cycle
Clock Stop Cycle
The clock stop cycle is generated during bus data-in and bus data-out transfers when the chip set must wait for a REPLY from the lSI-11 bus before it can continue. It is also used to prevent the chip set from continuing past the address microcycle portion of a bus cycle when a DMA device has bus "mastership." For a clock stop cycle, the bus control PROM generates ClK STUT Hand ClK HOLD H. The ClK STUT H signal stretches the clock-high time from two to three high-frequency clock cycles. The ClK HOLD H Signal is clocked into a flip-flop (the ClK STOP flip-flip-flop) every cycle after two cycles of the high-frequency clock. The output of this flip-flop, ClK STOP, goes low and
55
Chapter 3-LS/-11 123 Processor
holds MCLK H In the high state until the CLK STOP flip-flop Is cleared.
In the case of a bus data-in or data-out cycle, the flip-flop is cleared 200 ns after REPLY has been received from the addressed device, or, in the DMA case, 130 ns after the DMA device has given bus masterhip back to the processor. This cycle is shown in the figure.
65ClK H
MClK H
J 'f
"
E65H~ r(
"
L-((
E130 H
"
L
{f E195 H
"
((
ClK STUT H II
ClK STOP
Clock Stop Cycle Memory Management Cycle
This cycle occurs during address microcycles when the memory man-agement chip is present and is enabled to do address relocation (en-abling of the MMU is under software control). The MMU chip signals to the processor board that it wants to do address relocation by asserting the MIS line MME L at the end of clock-high time of an address mlcro-cycle. The relocation circuit, shown in the figure, detects the MME L signal and causes MME HOLD to be asserted high 65 ns into clock-low time of the address microcycle. MME HOLD holds MCLK in the clock low state for a total of five high-frequency clock periods or 325 ns. A pulse is produced 195 ns into clock-low time which passes through the OR gate and causes DALFF CLK to latch the relocated address, driven out of the MMU chip onto theDAL bus at this time, into the DAL driver flip-flops. Since the BDAL bus Is continuously enabled during this time, the relocated address is immediately driven onto the BDAL lines.
The relocation timing circuitry automatically clears itself after five high-frequency clock periods and releases MME HOLD which im-mediately allows MCLK H to go high, ending clock-low time.
Reset Cycle
The final variation of the basic cycle is when a CHIP RESET occurs.
CHIP RESET is generated by the circuit shown in the figure and occurs for anyone of five error conditions that warrant immediate attention by
56
Chapter 3-LSI-11 123 Processor
the chip set. RESET H is enabled 65 ns into clock-low time and causes the ring oscillator to stretch clock-low time from two periods of the high-frequency clock to three. This extended clock-low time allows CHIP RESET to initialize the MOS/LSI chips.
MIB15' MMEL
MCLK L
Relocation Timing Circuit
CTL ERR H
PAR ERR H
DCLO H
ABORT H
Reset Circuit
Chip Reset/RESET
RESET is routed to air MOS chips except the MMU. If an interrupt requiring immediate attention occurs, the line is asserted high. The following five interrupts require immediate attention.
1. Control error - Nonexistent control chip selected by the micro-code. A trap to location 10aoccurs.
57
Chapter 3-LSI-11 123 Processor
2. Bus error - Nonexistent memory location aooessed. A trap to location 480ccurs.
3. Parity error - A parity error detected on a current read from memory. A trap to location 1148occurs.
4. MMU abort - The MMU has aborted a mapped reference. A trap to location 25080ccurs for any of the following reasons.
The memory location referenced Is not present In the current user's protected address space.
An attempt Is made to modify a write-protected location.
The user Is exceeding his allotted page boundary.
5. DC Power-Up - Upon power-up the processor forces two se-quential RESETS to the chip set to Initialize all Internal chip regis-ters. The dc power .. up line than clears and Is not activated again while dc power Is on.
CONFIGURATION