Characteristics of the Fabricated Inverter

The inverter including gate driver, presented in subsection 3.2.2, occupies an area of 2.61 x 1.31 mm². The majority of the chip area is occupied by the HV output DMOS transistors DM1, DM2 and DM3 since they have to deliver high output currents for the capacitive load. ESD protection for the high voltage inputs and outputs is also area consuming. The spread spectrum clock generator presented in subsection 3.3.2 occupies an area of 1.470 x 0.645 mm². It is positioned as close as possible to the inverter to force influences.

The stack of two wafers in thick SOI leads to an increased height of the IC. The overall height of the implemented HVIC was measured to 740µm. Due to the thickness, modern package types such as quad-flat no-leads (QFN) packages cannot hold the IC which is why it was bonded into a dual-in-line package with 32 pins (DIL32). A printed circuit board (PCB) was designed to deliver the appropriate input signals for the purposes of research as shown in Figure 3.40b.

3.4. Implemented High Voltage Integrated Circuits 49

To ensure sufficient lifetime of the dies, measurements were only performed up to±200 V. Figure 3.41a shows the measured output signal of the inverter which proves that it is able to drive capacitive loads with up to±200 V at 5 kHz. The voltage was measured with a high voltage probe of type "TT-HV 250"

from TESTEC Elektronik GmbH with an attenuation ratio of 100:1 [104]. It can be seen that all three states, positive high voltage supply, negative high voltage supply and ground, can be attained. The related output current was measured with a differential probe across a resistor of 10.3Ωof type "TT-SI 9001"

from TESTEC Elektronik GmbH [105]. An attenuation ratio of 10:1 was used. For an output load of 1 nF the peak output current was measured to -396.12 mA as shown in Figure 3.41b. The maximum output current for the fabricated inverter was measured for an output load of 10 nF. The measured 442.72 mA is 3.18 % smaller than the simulated peak current. Figure 3.41b also shows that the output current is limited for the return-to-zero transition resulting in a low slew rate of the output voltage.

(a)Output voltageV_out. (b)Output current I_out.

Figure 3.41.:Measured output characteristic of the fully integrated three-state inverter. Measurement was performed with an output load of 1 nF and a high voltage of±200 V.

Figure 3.42 shows the measured and simulated rising and falling edge of the high voltage pulse generator output voltage for voltages up toV_±HV=±200 Vand an output load ofC_L=10 nF. It can be seen that the slope of the measurement differs significantly from the nominal simulation. An analysis of the process control monitoring for the production run of this specific IC confirms the deviation. In fact, the production run for this IC had to be restarted due to poor quality of the measured device parameters. The evaluation of the fabricated devices revealed that the threshold voltages of the high and low voltage transistors are approximately 10 % lower than in the nominal simulation. For the resistances, the investigations revealed deviations of -8 % from the nominal value. Hence, the resistors can be better approximated by worst power corners. By simulating the process corner, the measurement can be predicted better.

50 3. Implementation of SoCs with Ultra High Voltage Pulse Generator and Low Voltage Sensor Excitation

(a)Rising edge. (b)Falling edge.

Figure 3.42.:Comparison of measurement and simulation corners for the inverter output voltageV_outfor C_L=10 nFandV_±HV=±200 V.

Figure 3.42 shows the falling and rising edges for the maximum output load of 10 nF and a voltage change of 400 V_PP which result is a minimum slew rate and a maximum rising time. For this case, Table 3.5 lists the comparison of the measured and simulated slew rates. Slew rates of up to 39.35Vµs⁻¹ can be achieved for the maximum load which is about 21.30 % higher than the value simulated for the particular process corner.

Table 3.5.:Comparison of measured and simulated slew rate of the inverter outputV_outfor a high supply voltage of±200 V and an output load of 10 nF.

Rising edge Falling edge

measurement simulation measurement simulation SR₁₀₋₉₀

Vµs⁻¹

37.67 31.26 37.98 31.32

The minimum rising time was obtained for low magnitudes of the output voltage and a minimum capacitive load connected to the output. For 1 nF and an output voltage change of 100 V_PP a maximum slew rate for the rising edge was measured to 99.56Vµs⁻¹. The corresponding rising time was measured to 1.00µs. The slew rate for the falling edge is limited to 45.46Vµs⁻¹. The simulated value of 113.57Vµs⁻¹ is about 2.50 times higher than the measurement which can be traced back to production-related deviation and parasitic turn on of the high-side transistor.

The inverter was successfully connected to an electroluminescent device. The lighted EL is shown in Figure 3.43a. In addition, the inverter was connected to an ultrasound pulser of type MA40S4S [106]

which represents a load of 2.55 pF. An output frequency of 40 kHz and supply voltages of V_±HV=±10 V were achieved by the implemented inverter. The transmitted ultrasound signal was detected by a MA40S4R [106] as shown in Figure 3.43b. For the prove of concept the magnitude of the received signal is secondary since it is strongly dependent on the distance. Hence, the inverter can be used to drive capacitive loads.

3.4. Implemented High Voltage Integrated Circuits 51

(a)Fabricated inverter is driving a pad-printed electroluminescent device.

(b)Measured output signal of a received ultrasound wave.

Figure 3.43.:Prove of functionality of the inverter output for different applications.