Channel sounder implementation

Figure 2.3: HIRATE platform

The antenna transfer function and antenna gain are not part of the calibration procedure as stated above. They are measured in a separate step, as described in Section 2.3.5 and are then applied on the measured channel during post-processing, assuming perfectly matching impedances of the calibration network and the antennas.

2.3 Channel sounder implementation

The hardware platform used for the measurement campaigns presented in this thesis is the HIRATE (High Performance Digital Radio Testbed) platform shown in Figure 2.3 [KKPW13]. It is based on a custom build FPGA platform and has two parallel transmitter and receiver chains, each with 250 MHz bandwidth. It also features frequency synthesizers and IQ-modulators and demodulators for the lower GHz range.

The platform contains a firmware that takes care of timing and triggering, AGC, averaging and storage of received signals. The recorded signals are stored to on-board memory and offloaded to a connected PC after the measurement run is completed. The calculation of the channel impulse response is done in a post-processing step on the recorded data.

In the rest of this section I describe the hardware implementation.

2.3.1 Sounding sequences

The signal s ( t ), derived from the sequence s [ n ], should adhere to certain requirements to perform the best channel measurement possible. It should be maximally flat in the frequency domain over the entire bandwidth under investigation. The estimation of the channel impulse response relies on the

17

2 Channel sounder design and implementation

autocorrelation of the sequence. It should therefore ideally have an impulse-like periodic autocorrelation function. Such sequences exist and are called perfect [Lük88] and their autocorrelation function φ

_n

is equal to the signal energy at n = 0 and zero everywhere else [JP99].

Frank et al. provided a method to generate polyphase codes that adhere to these properties [FZH62]. A generalization to sequences of any length N

ZC

∈ N was given by Chu [Chu72]. These sequences, called Zadoff-Chu or Frank-Zadoff-Chu sequence, can be seen as multitone sequences with constant amplitude and perfect autocorrelation properties. One period of the sequence can be constructed as

s

_u

[ n ] = e

^{−jπun(n+1)/NZC}

(2.7)

with 0 ≤ n < N

_ZC

, 0 < u < N

_ZC

∧ gcd ( N

_ZC

, u ) = 1, n, u ∈ Z, where gcd ( a, b ) is the greatest common divisor of a and b . The constant amplitude of the complex sequence is a desirable property, as it allows a linear operating point of the transmit power amplifier with very low power backoff. In this work, sequences of length N

_ZC

= 256 and N

_ZC

= 1024 were used. The sampling rate was fixed at f

_s

=

¹

/

Ts

= 250 MHz, resulting in sequence period of T

_p

= 1 . 024 µ s and 4 . 096 µ s.

2.3.2 Timing reference and synchronization

The correlation based method for channel sounding relies on time synchroniza-tion between the transmitter and the receiver side. Ideally, all clocks on each side should be phase locked to a single reference. This comprises the following clocks:

• DAC clock (transmit sequence)

• Transmitter intermediate frequency (IF) & radio frequency (RF) local oscillators (see Section 2.3.3)

• Receiver IF & RF local oscillators (LO)

• ADC clock (receiver sampling)

A frequency offset between the DAC clock and the ADC clock directly translates to a timing and phase offset of the estimated channel impulse response that grows linear over time. An offset between the IF & RF local oscillators only affects the phase of the received signal.

18

2.3 Channel sounder implementation

Transmitter Receiver

Reference

clock reference cable

(a) Cable reference

Transmitter Receiver

Rubidium clock

synchronization only

Rubidium clock

(b) Rubidum clock

Figure 2.4: Clocking options

Figure 2.4 shows the two options that were used for the measurements in this work. The cable reference shown in Figure 2.4a uses only one reference clock (100 MHz in that case) that is distributed to the receiver side via a cable. All other clocks are derived from this reference signal using phase locked loops (PLL). Having a cable between transmitter and receiver is cumbersome, especially when the receiver is moved along busy sidewalks. It also limits the scenarios, as the cable cannot easily span across busy streets.

Time synchronization between transmitter and receiver can also be achieved with short term stable frequency standards. This clocking option is shown in Figure 2.4b. An independent rubidium clock is used as reference signal on both sides. At the beginning of a measurement, before performing the calibration, the two clocks need to be synchronized. This is performed by defining one clock as the master and the other as a slave, adjusting its frequency to be phase locked to the master via a cable. The cable is then removed and transmitter and receiver can be moved around independently from each other. The rubidium clocks used are described in [Wis07].

The channel snapshot measurement is triggered at fixed intervals which are multiples of the sequence length (see Section 2.1). This is implemented using a counter in the FPGA that is also clocked from the reference clock.

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2 Channel sounder design and implementation

I, Q

DAC 2 ch.

rubidium oscillator

MOD

PA Synth.

MOD BPF Synth.

LPF

10 MHz

Figure 2.5: Transmit signal generation

2.3.3 Transmit signal generation

The transmitter side of the channel sounder follows a straightforward approach.

The block diagram is shown in Figure 2.5. A two channel digital to analog converter (DAC) generates the inphase (I, real) and quadrature (Q, imaginary) parts of the transmit sequence. This signal is fed into a first modulator that is driven by a local oscillator (Synth.) with the intermediate frequency (IF) signal. This signal is then fed into a second modulator. A band-pass filter (BPF) or high-pass filter is used to eliminate the unwanted side band. This signal is fed into a power amplifier (PA), connected to the transmit antenna.

A common reference clock is used to derive the sampling clock of the DAC as well as the local oscillator (Synth.).

The baseband source used in this work was either the HIRATE platform or a Rohde & Schwarz AFQ100B. In both cases the transmit sequence previously described is continuously played from memory with a fixed sample rate of 250 MHz. The first modulator is part of the HIRATE platform and based on a MMIC design. The second modulator must be chosen according to the desired frequency band. The filter also depends on the frequency band and was either an integrated coaxial module (below 30 GHz) or a waveguide filter.

The local oscillator clock signals are generated using low phase noise frequency generators.

An alternative approach was used for the signal generation of the measure-ments described in Section 4.6. A Rohde & Schwarz SMW200A signal generator was used. It was fed with the baseband signals and the reference clock and performed the upconversion, filtering and power amplification of the 28.5 GHz signal.

2.3.4 Received signal sampling

The receiver chain is set-up as a superheterodyne receiver, as shown in Figure 2.6. A low noise amplifier (LNA) and an optional band-pass filter amplify the

20

2.3 Channel sounder implementation

BPF BPF LPF

Synth.

rubidium oscillator

ADC

LNA VGA 2 ch

10 MHz

Synth.

Figure 2.6: Receiver chain

received signal from the antenna and remove unwanted out-of-band interference.

A first demodulator stage is used to convert the received signal to a lower intermediate frequency, where it is filtered and amplified again. A second stage with an I/Q demodulator is then used to generate the baseband signal that is fed into the analog-to-digital converter.

The first LNA, filter and demodulator stage is set-up from discrete com-mercially available components for each frequency band. The second stage, including the variable gain amplifier (VGA) is integrated in the HIRATE plat-form with a tunable IF frequency in the order of 2 GHz. The low-pass filter in front of the ADC is used to remove any remaining out-of-band signals and to avoid aliasing effects.

The FPGA that processes and stored the received samples is not shown in this figure. It is however also connected to the VGA and an automatic gain control (AGC) is implemented in the digital domain. The power levels at the ADC inputs are monitored and the VGA is controlled to guarantee a high input level without clipping. The snapshot timing and the averaging is also performed in digital domain and controlled by the FPGA. The recorded snapshots are stored in on-board RAM and are downloaded to a connected PC after completing the measurement run.

2.3.5 Antennas

The antennas are the interface between the transmitter, receiver and the wireless channel itself. Their radiation pattern and polarization have a direct influence on the measured and estimated channel.

Ideally, the antenna would have an isotropic pattern, radiating with equal gain in all directions. Then, the channel measurement would include the propagation effects in all spatial directions around the transmitter and receiver.

Isotropic radiators are however only a theoretical concept and cannot be fully realized in real hardware. As the environments under investigation in this

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2 Channel sounder design and implementation

(a) 10 GHz Antenna (b) 28 GHz Antenna

Figure 2.7: Antenna designs

work are of an urban outdoor nature, omnidirectional antenna patterns with the main lobe in the horizontal plane and a large enough opening angle in elevation direction can be assumed to be a good approximation to measure their channels. Thus, the requirement for the antenna pattern reduces to uniform gain in azimuth direction as well as uniform gain in the relevant part of the elevation region above and below the horizon.

A half-lambda dipole antenna is a good approximation to these requirements for vertical polarization. For horizontal polarization however, more complex designs are needed, for example the Alford loop [AK40].

For the measurements in this work, vertical polarization was chosen and antennas for 10 GHz and 28 GHz were built. They are shown in Figure 2.7a and 2.7b respectively. They are constructed based on semi-rigid coaxial cable as quarter-lambda monopoles. The inner conductor serves as the monopole and a copper sheet is soldered to the outer conductor to serve as a reflecting plane that matches the antenna impedance to the coaxial cable impedance of 50 Ω. Opposed to a full dipole, the pattern of these antennas is asymmetric in elevation direction.

Figures 2.8 and 2.9 show the patterns of both antennas in azimuth and elevation direction. I measured these patterns using a vector network analyzer and an automated rotation positioner. Both antennas exhibit a relatively uniform gain in azimuth direction, which is in line with the requirement.

The visible residual variation can be attributed to imperfections of the inner

22

Im Dokument Channel investigation of outdoor millimeter-wave access links (Seite 33-39)