VCO Buffer Tree

Figure 6.11 Block diagram of buffer tree

In practice, the VCO is supposed to deliver two outputs. One output is for the feedback loop of the frequency synthesizer, the other one goes to the transceiver. In order to provide a differential signal at both outputs, a VCO buffer tree is designed.

On the other hand, it also helps to boost the signal power. It is of great significance since the correct operation of frequency dividers in the synthesizer and the mixer in the transceiver both require a high power LO signal. Its simplified block diagram is shown in Figure 6.11. All the amplifiers in the buffer tree are built with the cascode topology. The cascode topology could offer sufficient reverse isolation to the VCO, to ensure its stable operation.

The schematic and design parameters of the buffer tree are illustrated in Figure 6.12. All amplifiers are differential, but only the half-circuit is shown. The first stage buffer S1 employs a small size in order to prevent overloading the VCO.

Following S1, two buffer amplifiers S2 and S3 have the same size, giving two

differential outputs. Buffer S3 is designed for outputs delivered to the transceiver. Its output impedance is matched to 50 Ω for measurement purposes. Another buffer S2 provides outputs for the 32:1 divider chain. Its output impedance is matched to the conjugate impedance of the ILFD’s input impedance. Since the ILFD only has a single-ended input, another output of buffer S2 is connected to a dummy network which has the same impedance with the ILFD’s input impedance.

Figure 6.12 Half-circuit of the buffer tree

From past knowledge of this technology, the amplifier would experience a frequency shift to higher frequencies, when it is measured. Thus in the design phase, the peak of the output power is deliberately designed to be around 38 GHz. Hopefully

when it is measured, the operation bandwidth of this buffer tree is centered on 41 GHz.

Meanwhile the maximum output power exists at around 40 GHz. The simulated performance of the designed buffer tree is characterized in Table 6.6. The simulated and measured output power will be presented in the following chapter.

Table 6.6 Simulated Performance of buffer tree

Power supply 1.2 V

Vg 0.75 V

Current consumption

4.5 mA (S1) 12.5 mA (S2) 12.5 mA (S3) Output power

(output of Buffer S3) ≥ -6 dBm

6.3.3. 32:1 Frequency Divider Chain

40 GHz injection locked frequency divider

The first stage frequency divider of the 32:1 divider chain is built as an injection locked frequency divider. At 40 GHz frequency range, the injection locked frequency divider achieves a good balance between the locking range and power consumption. Figure 6.13 shows the simplified schematic of the circuit. The bias circuit for the input transistor M3 is not included here. It uses the topology of a direct injection locked divider. The input signal is injected directly into the oscillator core through the transistor M3. The frequency of the output signal is locked at half the frequency of the input signal.

Figure 6.13 40 GHz ILFD

Table 6.7 Design parameters of 40 GHz ILFD

I_tail 3 mA

L₁, L2 460 pH Q-factor

(inductor) 15 @ 40 GHz M₃ 7 × 2 µm × 100 nm M1, M2 5 × 2.1 µm × 100 nm

The design begins with a free-running oscillator at 20 GHz. It has been proved that the wide locking range of the ILFD requires a large tank inductor with a low Q-factor [84]. From EM simulations, the tank inductors (L1 and L2) are 460 pH at 20 GHz with a Q-factor of 15. The choice of M3 size is a compromise between the gain of the injection path and the induced parasitic elements. High injection gain requires a large M3. However, its large parasitic capacitance would in turn attenuate

the injected power. By careful simulations, the size of M₃ is fixed at 14 µm / 100 nm.

It is also biased with supply voltage V_DD for the highest gain.

4-stage static dividers

Figure 6.14 Block diagram of the 16:1 SFD

The 4-stage static frequency divider (SFD) follows the 40 GHz ILFD to achieve the division-by-16 from 20 GHz to 1.25 GHz. Each stage SFD is composed of two cascaded CML latches with a reversed feedback, as shown in Figure 6.14.

Figure 6.15 First stage static divider

Figure 6.16 Second stage static divider

Figure 6.17 Third and fourth stage static divider

To speed up the operation of the latch, the current source transistor in the conventional CML latch is removed. This topology is usually called the ‘class-AB’

latch. It provides two upsides. Firstly, it saves voltage head-room under a 1.2 V supply voltage. Furthermore, the input transistors operate in a sort of class-AB mode, like the class-AB power amplifier. When the rising edge of the input signal comes, more current flows into the latch. It is helpful to speed up the switching operation of the latch. The four stage static dividers are shown respectively in Figure 6.15, Figure 6.16 and Figure 6.17. The power consumption of the each stage divider is scaled down with decreased operation frequency. Similarly, the size of active devices

is scaled up. They are designed with optimized power and bandwidth with respect to the corresponding operation frequency. After the second stage static divider, the operation frequency decreases to 5 GHz. The last two stage static dividers share the same design.

Simulated performance

Figure 6.18 Simulated transient output of 32:1 frequency divider chain

The whole divider chain circuit is simulated with simulator goldengate in cadence. The interconnection wires in the layout have been EM-simulated with the Ansoft HFSS. By using the s-parameter data of these interconnection wires in the schematic design, the parasitic components of the layout were taken into account.

This is of great importance to achieve the correct operation of frequency dividers in the interested band. Figure 6.18 shows the simulated output signal of each stage frequency divider. The power of the input signal is -2 dBm, which is the estimated output power of the VCO’s buffer tree. Apparently, the function of the 32:1 frequency division is achieved. Its performance is summarized in Table 6.8.

Table 6.8 Performance summary of 32:1 divider chain

Power supply 1.2 V

Input power -2 dBm

Current consumption

3.6 mA (ILFD) 4.2 mA (1st stage SFD) 3.4 mA (2nd stage SFD) 1.7 mA (3rd, 4th stage SFD) Locking range

(40 GHz ILFD alone) 36 – 45 GHz

Locking range

(32:1divider chain) 37 – 44 GHz