This group of instructions provides you with BCD arithmetic operations using the Ar1 and Ar2 registers.
In general, the instructions associate the Ar1 register with "X" and the Ar2 register with "Y" in the mnemonic for the instruction. Both registers contain values which are considered BCD full-precision values when operated upon by instructions in this group.
The mantissas referred to below consist of 12 BCD digits. All the shifting operations manipulate the digits as units (Le., 1 digit - or 4 bits - at a time). In addition, shifting operations involve an additional digit in the A register (located in the lower 4 bits, numbered 0 through 3).
All arithmetic is performed in BCD. The values being operated upon are assumed to be nor-malized BCD floating-point (full-precision) values. Signs and exponents are left strictly alone.
There is a flag in the processor, called Decimal Carry, which is set when an overflow occurs during a BCD operation.
A full discussion of BCD arithmetic techniques can be found in Chapter 5.
Instruction Description
Mantissa right shift on Arl. The number of digits to be shifted is specified in the lower 4 bits (0-3) of the B register. The shift is accomplished in three stages
-1. The digit in bits (0-3) of the A register is right-shifted into the first digit of the mantissa, with the twelfth digit being lost. This is the first shift.
2. The mantissa digits are then right-shifted for the remaining number of digits specified. The twelfth digit, except for the last shift, is lost on each shift and the vacated digits are zero-filled.
3. Finally, the last right-shift takes place with the twelfth digit shifting into the A register. The Decimal Carry flag in the processor is cleared along with the upper 12 bits of the A register (4-15).
Instruction Description
Mantissa right-shift on Ar2. The number of digits to be shifted is specified in the lower four bits (0-3) of the B register. The shift is accomplished in three stages
-1. The digit in bits (0-3) of the A register is right-shifted into the first digit of the mantissa, with the twelfth digit being lost. This is the first shift.
2. The mantissa digits are then right-shifted for the remaining number of digits specified. The twelfth digit, except for the last shift, is lost on each shift, and the vacated digits are zero-filled.
3. Finally, the last right-shift takes place, with the twelfth digit shifting into the A register. The Decimal Carry flag in the processor is cleared along with the upper 12 bits of the A register (4-15).
Mantissa left-shift on Ar2 for one digit. This is a circular shift, with the digit in bits (0-3) of the A register forming a thir-teenth digit. The non-digit part of the A register is cleared (Le., bits 4-15), and the Decimal Carry flag in the processor is cleared.
Mantissa right-shift on Ar1 for one digit. The twelfth digit is shifted into the A register (bits 0-3). The non-digit part of the A register is cleared (Le., bits 4-15), and the Decimal Carry flag in the processor is cleared. The first digit in the mantissa is set to O.
Normalizes the Ar2 mantissa. The mantissa digits are left-shifted until the first digit of the mantissa is non-zero, or until twelve shifts have taken place, whichever comes first. If the original first digit is already non-zero, no shifts occur. The number of shifts required is stored as the first four bits (0-3) of the B register. If twelve shifts were required, the Decimal Carry flag in the processor is set, otherwise it is cleared.
Ten's complement of Ar1. The mantissa of Ar1 is replaced with its ten's complement and Decimal Carry is cleared.
Instruction with its ten's complement and Decimal Carry is cleared.
Fixed-point addition. The mantissas of Ar1 and Ar2 are added together, and the result is placed into Ar2. Decimal Carry is added to the twelfth digit. After the addition, Decimal Carry is set if an overflow occurred, otherwise Decimal Carry is cleared.
r-yiantissa word addition. The contents of the B register are added to the ninth through twelfth digits of the mantissa of Ar2. Decimal Carry is added to the twelfth digit; if an over-flow occurs, Decimal Carry is set, otherwise it is cleared.
Fast Multiply. Performs the multiplication by repeated addi-tions. The mantissa of Ar1 is added to the mantissa of Ar2 a specified number of times. The number of times is specified in the lower 4 bits (0-3) of the B register. The result accumulates in Ar2. If intermediate overflows occur, the number of times they occur appears in the lower 4 bits of the A register after the operation is complete. The upper 12 bits of the A register are cleared along with Decimal Carry.
Fast divide. The mantissas of Ar1 and Ar2 are added together until the first decimal overflow occurs. The result accumulates into Ar2. The number of additions without overflow is placed into the lower 4 digits of the B register (0-3). The remainder of the B register is cleared, as is the Decimal Carry flag in the processor.
Clears the Decimal Carry flag in the processor.
Skips to {address} if Decimal Carry is set. Decimal Carry is a flag in the processor which may be set as the result of certain BCD arithmetic operations (see Chapter 5 for details).
Skip to {address} if Decimal Carry is cleared. Decimal Carry is a flag in the processor which may be set as the result of certain BCD arithmetic operations (see Chapter 5 for details).
I/O Group
The I/O group of instructions provides you with some of the operations necessary to accessing peripheral devices through the I/O bus. In addition to the instructions contained here, there are instructions in other groups which can have I/O effects (e.g., LOA, STA ... ).
The techniques useful to the implementation of I/O operations using the instructions in this group and the other groups are discussed in Chapter 7.
Instruction
::;FC {address}
::;::s
{address}:::sc:
{address}=:"Yi T
._:J_~ .i.
Description
Skips to {address} if the Flag line is set (ready). The Flag line is associated with a peripheral on the current select code (see Chapter 7 for details).
Skips to {address} if the Flag line is clear (busy). The Flag line is associated with a peripheral on the current select code (see Chapter 7 for details).
Skips to {address} if the Status line is set (ready). The Status line is associated with a peripheral on the current select code (see Chapter 7 for details).
Skips to {address} if the Status line is clear (busy). The Status flag is associated with a peripheral on the current select code (see Chapter 7 for details).
Enables the interrupt system. Cancels the DIR instruction.
Disables the interrupt system. Cancels the EIR instruction.
Sets DMA outwards. Directs that DMA operations read from memory, write to the peripheral.
Sets DMA inwards. Directs that DMA operations read from the peripheral, write to memory.
Enables the DMA mode. Cancels the DDR instruction.
Disables Data Request. Cancels the DMA instruction.
Miscellaneous
The following instructions cannot be classified into any of the other groups.
Instruction
E>:E {value} [, I]
Description
Null operation. This is exactly equivalent to LOA A.
The contents of any register can be treated as the current instruction and executed. {value} is a numeric expression in the range 0 through 31, indicating the register to be used.
The register is left unchanged, unless the instruction code causes it to be altered. The next instruction to be executed is the one in the word following the EXE, unless the code in the executed register causes a branch.