The distribution version of CP/M-86 is setup for operation wi th the Intel· SBC 86/12 microcomputer and an Intel 204 diskette controller •. All hardware dependencies are, however, concentrated in subroutines which are coliectively referred to as the Basic I/O System, or BIOS. A CP/M-86 system implementor can modify these subroutines, as described below, to tailor CP/M-86 to fit nearly any 8086 or 8088 operating environment. This section describes the actions of each BIOS entry point, and defines variables and tables referenced wi thin the BIOS. The discussion of Di sk Oef ini tion Tables is, however, treated separately in the next section of this manual.
5.1 Organization of the BIOS
The BIOS portion of CP/M-86 resides in the topmost portion of the operating system (highest addresses) , and takes the qeneral form shown in Figure 5-1, below:
CS, OS, ES, SS:
Console Command Processor
and Basic Disk Operatinq System
~S + 2500H: BIOS Jump Vector CS + 253FH:
BIOS Entry Points BIOS:
Disk Parameter
'rab1es Uninitialized
Scratch RAM
Figure 5-1. General CP/M-86 Organization
CP/M-86 System Guide 5.1 Organization of the BIOS As descr ibed in the following sections, the CCP and BDOS are supplied with CP/M-86 in hex file form as CPM.H86. In order to implement CP/M-86 on non-standard hardware, you must create a BIOS which performs the functions listed below and concatenate the resulting hex file to the end of the CPM.H86 file. The GENCMD utility is then used to produce the CPM.SYS file for subsequent load by the cold start loader. The cold start loader that loads the CPM.SYS file into memory contains a simplified form of the BIOS, called the LDBIOS (Loader BIOS). It loads CPM.SYS into memory at the location defined in the CPM.SYS header (usually 0400H). The procedure to follow in construction and execution of the cold start loader and the CP/M-86 Loader is given in a later section.
Appendix D contains a listing of the standard CP/M-86 BIOS for the Intel SBC 86/12 system using the Intel 204 Controller Board.
Appendix E shows a sample" skeletal" BIOS called CBIOS that contains the essential elements with the device drivers removed. You may wish to review these listings in order to determine the overall structure of the BIOS.
5.2 The BIOS Jump Vector
Entry to the BIOS is through a "jump vector" located at offset 2500H from the base of the operating system. The jump vector is a sequence of 21 three-byte jump instructions which transfer program control to the individual BIOS entry points. Although some non-essential BIOS subroutines may contain a single return (RET) instruction, the corresponding jump vector element must be present in the order shown below in Table 5-1. An example of a BIOS jump vector may be found in Appendix D, in 'the standard CP /M-86 BIOS listing.
Parameters for the individual subroutines in the BIOS are passed in the CX and DX registers, when required. CX receives the first parameter: DX is used for a second argument. Return values are passed in the registers acco ding to type: Byte values are returned in AL. Word values (16 bits) are returned in BX. Specific parameters and returned values are described with each subroutine.
CP/M-86 System Guide 5.2 The BIOS Jump Vector write Console Character Out Write Listing Character Out Write Char tb Punch Device Read Selected Sector Write Selected Sector Return List Status (re) initialization subroutines, simple character I/O subroutines, and disk I/O subroutines.
5.3 Simple Peripheral Devices
All simple character I/O operations are assumed to be performed
CP/M-86 System Guide 5.3 Siml?le Peripheral Devices Table 5-2. CP/M-86 Logical Device Characteristics
Device Name
I
CharacteristicsCONSOLE The principal interactive console which communicates with the operator, accessed through CONST, CONIN, and CONOUT. Typically, the CONSOLE is a device such as a CRT or Teletype.
LIST
PUNCH
READER
The principal listing device, it it exists on your system, which is usually a hard-col?Y device, such as a printer or Teletype.
The l?rincipal tape punching device, if it exists, which is normally a high-speed paper tape punch or Teletype.
The principal tape reading device, such as a simple optical reader or teletype.
Note that a single peripheral can be assigned as the LIST, PUNCH, and READER device simultaneously. It no peripheral device is assigned as the LIST, PUNCH, or READER device, your r.BIOS should give an appropriate error message so that the system does not "hang"
if the device is accessed by PIP or some other transient proqram.
Alternately, the PUNCH and LIST subroutines can ;ust simply return, and the RF~DER subroutine can return with a lAH (ctl-Z) in ~eq A to indicate immediate end-ot-file.
For added tlexibility, you can optionally implement the
"IOBYTE" function which allows reassignment ot physical and logical devices. The IOBYTE function creates a mapping of logical to physical devices which can be altered during CP/M-86 processing (see the STAT command). The detinition of the IOBYTE function corresponds to the Intel standard as follows: a single 10cati6n in the BIOS is maintained, called IOBYTE, which detines the logical to physical device mapping which is in etfect at a particular time.
The mapping is performed by splitting the IOBYTE into four distinct fields of two bits each, called the CONSOLE, READER, PUNCH, and LIST fields, as shown below:
most significant least significant IOBYTE