This appendix contains a discussion of the principles of synchronous serial data transmission and reception, followed by descriptions of the synchronous receivers and transmitters used in the DVII Synchronous Multiplexer.
C.I BINARY DATA TRANSFER METHODS
Bits of binary data are commonly transferred between digital machines by changes in current or volt-age. Data may be transferred in serial over a single line, or in parallel over several lines at once. The transfers may be synchronous, in which the exact departure or arrival time of each bit of information is predictable, or they may be asynchronous, in which case the data may be transferred at non-uniform rates. Aspects and applications of these data transfer modes will now be discussed.
C.I.I Parallel vs Serial
In parallel transmission, each bit of the set of bits that represent a character has its own wire. An additional wire called the "strobe" or "clock" lead notifies the receiver unit that all of the bits are present on their respective wires so that the voltages on the wires can be sampled. Figure C-I schemat-ically depicts the parallel transfer of the 8-bit character, 1100000 1.
+3V +3V
+3V +3V
OV 0 OV
OV 0 OV
OV 0 OV
OV 0 OV
OV 0 OV
+3V +3V
+:n
STROBEIT
30VMK-0814
Figure C-I Parallel Data Transfer
In serial transmission, the bits that represent a character are sent down a single wire one after the other.
Computers and other high-speed digital machines generally operate on parallel data, so data is trans-ferred in parallel between these devices wherever they are in close physical proximity. However, as the distance between the. devices increases, the multiple wires not only become more costly, but the com-plexity of the line drivers and receivers increases, due to the increased difficulty of properly driving and receiving signals on long wires.
Serial transmission is generally used where the cost of the communication medium (wires) is suf-ficiently high that a relatively complex transmitter/receiver system is justified. The more complex system will serialize the bits that represent the character, send them over a single line, and reassemble them in parallel form at the reception end.
Conversion from parallel to serial and from serial to parallel is typi"cally done with shift registers. In most data communications applications, serial transmission is preferable to parallel transmission.
C.l.2 Asynchronous vs Synchronous·
Because of the mechanism design in early serial teleprinters, and to facilitate fail-safe operation, serial teleprinter systems have adopted the convention that an idle line (no data being sent) is one in which current is flowing. Data transmission occurs when the current in the line is interrupted in a specified fashion. By convention,the idle (current flowing) state is called the I state or MARK condition, and the lack-of-current state is called the 0 state or SPACE condition. To start the receiving teleprinter mechanism, the line is brought to the 0 state for I-bit time. (This is called the START bit.) For the next eight successive bit times, the line is conditioned to a 1 state or 0 state, as required, to represent the character being sent. To allow the receiving teleprinter mechanism to coast back to a known position in time for the beginning (START bit) of the next character, one or more bit times of 1 state (idle) are sent. This period is called the STOP bit interval.
Except for the requirement that the line be idle for at least the STOP bit interval, the transmission of the next character can begin at any time. The lack of a continuous synchronous agreement between the transmitter and the receiver (specifically, the lack of a clocking signal within or accompanying the data channel) causes this type of transmission to be called asynchronous, literally, without synchronization.
A typical asynchronous receiver contains an interval clock and a system for detecting the I-to-O transi-tion that indicates the beginning of a start bit. The internal clock delays one-half bit time, checks to see that the start bit condition is still on the line and then makes eight successive samples, I-bit t~me apart, to determine the eight bits being sent.
Although modern asynchronous receivers do not require a stop interval for mechanism coasting pur-poses, they do require a stop interval to guarantee that each character will begin with a I-to-O transi-tion, even if the preceding character was all zero bits. This requirement for a I-to-O transitransi-tion, to indicate the beginning of each character, causes a complete character to require 10 bit times, only 8 of which contain real data. The other 20 percent of the line time is used strictly for timing purposes. The asynchronous character format is shown in Figure C-2.
Synchronous communications require either a separate rate clock lead from the transmission point to the reception point (in addition to the data lead) or a modem that includes the clock information with the data. In the case of a modem, the clock is recovered from the signal sidebands by the modem and is brought out of the modem as a separate lead. This indicates to the data communications hardware (typically a computer interface) the appropriate instant to sample the data on the received data lead.
The inclusion of the clock in the data stream or in a separate lead keeps the transmitter and receiver in sync, hence the term synchronous communication. Synchronous character format is shown in Figure C-3.
S 0 0 0 0 S
(LlNE1) DATA
(LINE 0)
y ~
1 1 t
STOP BITSDATA BITS START BIT
MK-0832
Figure C-2 Asynchronous Character Format
H
1 BITTIMEMODEM CLOCK
o o
o 0 0... - ...
0 o oDATA LSB
I I I
:+-
SYNC CHARACTER - ...J ....
1.t---DATA CHARACTER----"':I I I
Figure C-3 Synchronous Character Format
C.I.3 Synchronizing at the Receiver
MK-0833
Since start and stop bits are not required in synchronous communications, all bits are used to transmit data; therefore, there is not the 20 percent waste characteristic of asynchronous communication. How-ever, the character framing information provided by the start and stop bits is absent, so another inethod of determining which groups of bits constitute a character must be provided.
In Figure C-4, bits 1-8 might be one character and bits 9-13 part of another character, or bit 1 may be part of one character, bits 2-9 part of a second character, bits 10-13 part of a third charaGter, and so on. The delimiting or framing of each actual character is accomplished by defining a sync character.
The sync character is usually chosen such that its bit arrangement is significantly different from that of any of the regular characters being transmitted. Thus, when a sync character is preceded and followed by regular characters, there is no possible successive pattern of bits that equal the bit patterns of the sync character, except those eight bits that actually are the sync character.
MK-0826
Figure C-4 Serial Bit Stream
Typical synchronous receiver units are placed in a sync search mode by either hardware or software whenever a transmission begins, or whenever a data dropout has occurred and the hardware or soft-ware determines that resynchronization is necessary.
Synchronization is accomplished by the hardware shifting eight bits into a shift register and comparing those eight bits (as a parallel word) to the sync character which has been set in a register. If a match occurs, the receiver begins shifting in bits and raising a "character available" flag every eight bits. If no match is realized, the receiver shifts in a new bit from the line, shifts all bits recorded to date (thus shifting the oldest bit off the end), and does a new parallel comparison to the sync character. The process continues until the sync character is framed.
To decrease the probability that a receiver will synchronize on a bit combination that is not the intended sync character but rather a combination of other characters, synchronous receivers are fre-quently arranged to synchronize on two successive sync characters.
D.1 DDCMP