Anisotropic plasma etching profiles in silicon can be achieved by a number of different techniques; nevertheless the key feature always is the reduction of the lateral etching rate and/or the enhancement of the vertical etching rate. The available strategies are:
1. Adjustment of the ion-to-neutral (or more accurate: the ion-to-radical) ratio. This can be done by adjusting the flow ratio of radical precursors (e.g. SF6) to ion precursors with no chemical activity (e.g. noble gases such like argon) and/or by adjusting the excitation power, dc bias and operating pressure, in to generate a directed flux of energetic ions to the surface (fig. 4.12).
2. Etching in SF6/O2 plasmas at low substrate temperatures under ion bombardment (cryo etching). In this case, the spontaneous etching rate of fluorine with silicon is reduced, and the sidewall is partially oxidized, preventing the sidewall from chem-ical etching by fluorine. Ion bombardment of the bottom of the trench profile pro-vides the activation energy for the etching reaction (fig. 4.13).
This so-called cryo etching technique can have some disadvantages. It cannot be applied with photoresist masks, since photoresist produces cracks and delaminates at the required low sample temperatures. Therefore, it is required to deposit a so-called hard mask, like oxide or nitride, on the sample prior to lithography. The lithographic structures then must be transferred from the photoresist mask into the hard mask by an additional etching step. This arrangement therefore introduces a further process step which requires a longer total processing time. In order to maintain the low sample temperature despite the heat generated by the plasma, the ion bombardment and the reaction enthalpy, a sufficient thermal contact between sample and sample holder is required. Such thermal contact is provided for samples which have a flat backside surface, like wafers, but cannot be guaranteed for certain pre-processed MEMS samples, such like silicon membranes (refer to chapter 6).
In addition, hard masks usually introduce some intrinsic stress into the sample.
Although the stress of deposited hard masks can be eliminated by adjusting the deposition parameters (for instance, silicon nitride can be deposited with a wide range of intrinsic stress, from compressive to tensile, by adjusting the parameters of the PECVD deposition process), the different thermal expansion coefficients of hard mask and silicon might introduce some stress when the sample is cooled down from room temperature to cryo temperature.
Therefore, this cryo etching technique can be applied for wafer-type samples if smooth and flat sidewalls are required at relatively high etching rates. The applica-tion of such etching techniques for the fabricaapplica-tion of MEMS, however, introduces some disadvantages or technological problems, which do not seem to be apparent with the gas chopping etching technique.
3. Deposition of a sidewall passivation layer during the etching process under ion bombardment of the bottom of the trench (fig. 4.14). This can be done by adjusting the F/C ratio of fluorocarbon based discharges.
By setting the F/C value at 2 or below, polymer deposits on all substrate surfaces which are protected from energetic ion bombardment (see fig. 4.9). Since the ion flux is directed vertically to the sample surface by adjusting pressure and dc bias accordingly, the sidewalls of etching profiles are not hit by ions, but the bottom of
4.3. Anisotropic etching of silicon 39
F/O2 I+
SiF Ox y
SiF Ox y SiF Ox y
(a)
(b)
(c)
Figure 4.13: Anisotropy caused by low sample temperature. Due to the low sample temperature, the sponta-neous etching of fluorine with silicon reduces dramatically. This effect is enhanced by the addition of oxygen to the process gas mixture (a). Etch-ing proceeds only due to ion bom-bardment (ion-enhanced etching). Be-cause of the direct flow of ions, etch-ing proceeds only at the bottom, not at the sidewalls (a). Samples have been etched in an ICP reactor (Oxford In-struments Plasma Technology System 100) with a 90 sccm SF6/9 sccm O2 process gas mixture, 20 mTorr operat-ing pressure, 60 W ICP power, 40 V dc bias, and a helium backing of 15 Torr, at -60◦C (b) or -125◦C (c). The verti-cal etching rate reduces from 3 µm/min (b) to 0.5 µm/min (c) as the sample temperature decreases from -60◦C to -125◦C, but the anisotropy of the pro-file increases with decreasing sample temperature. The sample etched at -60◦C (b) still suffers considerable lat-eral etching due to the spontaneous etching reaction of fluorine with sili-con, which vanishes at a sample tem-perature of -125◦C (c).
the trench is. Therefore, the polymer film is constantly removed at the bottom of the trench by sputtering or ion-enhanced etching [65], leaving clean silicon available for etching with fluorine.
This situation is shown in figs. 4.15 and 4.16. For higher dc bias, and consequently higher ion energy flux to the sample, etching occurs even for low F/C values. This dependency between ion bombardment, F/C ratio and etching and deposition was
used to change the etching characteristics of silicon of a fluorocarbon discharge (SF6, CH4and CHF3) from isotropic to anisotropic, by varying the F/C ratio while maintaining a dc bias of 50 or 130 V to the sample. The flow rates of the feed gases have been largely varied. However, if anisotropy of the etched samples is plotted versus the F/C ratio calculated according to equation (4.11), all samples fit nicely in the trend. Anisotropy does not occur until the F/C value is≤2. The vertical and lateral etching rates also decreases with decreasing F/C value, where the lateral etching rate vanishes for F/C≤2, indicating that for F/C≤2 and no or only low ion energy flux deposition of polymer films rather than etching of silicon takes place. As a consequence, the anisotropy of the etching process increases to 1.
Etching and deposition are competing reactions taking place at the same time.
Therefore, as anisotropy increases, the etching rate decreases. Since this technique relies on the proper balance between etching and deposition, which are temperature dependent processes (fig. 4.11), anisotropy is lost when the sample temperature increases (see fig. 4.17). Sufficient thermal contact is provided for wafer-type sam-ple with a flat backside surface, but cannot be guaranteed for membrane-like or pre-processed MEMS samples (refer to chapter 6). Therefore, this etching tech-nique does not seem to be stable or reliable for the structuring of membranes for the fabrication of open-stencil masks, or similar MEMS devices.
A major disadvantage of all these approaches stems from the use of energetic ion bom-bardment and the competing reactions taking place. Energetic ion bombom-bardment in gen-eral reduces the etching selectivity to photoresist due to sputtering, resulting in mask erosion. Competing etching and deposition reactions reduce the etching rate, compared to the pure etching reacting alone, thereby increasing the required process duration and the etching selectivity.
Pure chemical etching of silicon (i.e. etching of silicon with fluorine) provides high selectivity to photoresist, due to the selective etching reaction, and potential high etching rates, if chemical active radicals (i.e. atomic fluorine) are supplied in sufficient quantities.
These conditions can be assured by adjusting process parameters like excitation power, operating pressure and flow rates of the precursor gases accordingly.
A so-called Gas Chopping Etching Technique transfers several advantages of isotropic, pure chemical etching of silicon (high selectivity to photoresist, high etching rate) to anisotropic etching profiles.
4.3. Anisotropic etching of silicon 41
F/CFx I+
F
(CF )x n (CF )x n
(a) (b)
(c) (d)
Figure 4.14: Anisotropy caused due to the deposition of a sidewall passivation layer (a).
The process gas mixture is adjusted for plasma deposition conditions on sample areas without ion bombardment. Ion bombardment of the bottom due to a directed flow of ions causes a constant removal of deposited film clusters due to sputtering. Therefore, the etching proceeds at the bottom, while lateral etching is suppressed, causing anisotropic profiles (a). The samples have been etched in an ICP etching reactor (Oxford Instruments Plasma Technology System 100) at 600 W ICP power, 130 V dc bias, 20 mTorr oper-ating pressure, 10◦C sample temperature and 15 Torr helium backing. The gas mixture was varied from 20 sccm SF6/25 sccm CHF3/0 sccm CH4 (b), to 20 sccm SF6/25 sccm CHF3/15 sccm CH4(c), and to 20 sccm SF6/25 sccm CHF3/20 sccm CH4(d), resulting in F/C ratios of 2.75 (b), 2 (c), and 1.4 (d). The rf power was adjusted to maintain a dc bias of 130 V. The vertical etching rate decreases from 600 nm/min (b) to 18 nm/min (c) to 7.5 nm/min (d), while the lateral etching rate decreases from 300 nm/min (b) to 0 nm/min (c, d). These experiments clearly demonstrate that vertical sidewalls do not appear until the F/C ratio is 2 or less (c, d). The transition from isotropic to anisotropic profiles appears for F/C ratios between 2 and 3 (refer also to fig. 4.16).
2 3 4 5 6 7 8 0.0
0.2 0.4 0.6 0.8 1.0
etching rate
etching rate [µm/min]
F/C ratio [1]
0.4 0.6 0.8 1.0
dc bias 50 V
anisotropy [1]
anisotropy
Figure 4.15: Etching rate and anisotropy for SF6/CH4/CHF3plasmas versus the F/C ratio.
1 2 3 4 5 6 7
0.0 0.2 0.4 0.6 0.8 1.0
dc bias 130 V etching rate
etching rate [µm/min]
F/C ratio [1]
0.4 0.6 0.8 1.0
anisotropy [1]
anisotropy
Figure 4.16: Etching rate and anisotropy for SF6/CH4/CHF3plasmas versus the F/C ratio.
The transition from isotropic to anisotropic etching appears for F/C ratios between 2 and 3.
4.3. Anisotropic etching of silicon 43
-40 -20 0 20 40 60 80 100 120 140 0
5 10 15 20 25 30 35 40
etching rate
etching rate [nm/min]
sample temperature [°C]
0.6 0.8 1.0
anisotropy [1]
anisotropy
Figure 4.17: Temperature dependence of the etching rate and anisotropy of an SF6/CHF3/CH4reactive ion etching process.