ADDRESS DECODE AND CPU I/O BUFFERS ••••.••••.••.••••

The Address Decode and I/O Buffer circuit enables the computer to pass information to and from the Double Density Disc Controller board.

In order for the board to be accessed, the following conditions must be met:

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1. The upper five address lines must match the selected base address.

2. The three lower address lines must be in the range of 0 through 4 or7.

3. Either I/O READ or I/O WRITE must be active low.

When these conditions are met the board can be accessed for read or write.

ADDRESS GATING

The addressing operation happens as follows: The upper five address lines are presented to IC46 where the user selects which section in the I/O address space he wishes the board to occupy. This is done by selectively inverting the proper lines in IC46. Once this has been done, when the computer sends this address to the board, IC4B-B will go low. This line is the Conditional Board Select (CBS) signal and is gated to the following: 1.

To the I/O Buffer Control Gate IC16-12. 2. To the enable input of IC33, the Port Select Decoder. The lower three addresses are presented to the port decoder through Latch IC45. Also the lower two address lines are buffered in IC1Bc,d and presented to the Controller IC29. IC33 generates all the conditional port select gating. If the lower three address lines are between 0 and 3, IC33 gates on IC32-B which in turn is inverted in IC17.

This inverted Controller Select(CS) signal partially enables ICts 18a and 18b. If the lower three address lines were decoded in IC33 to be equal to 4, The RW4 signal is generated which partially enables ICts 31a and 31b. If the lower three address lines were decoded to be 7, The SEVEN signal is generated. This SEVEN signal is passed to the Wait logic.

We have at the present selected one of three things. We have generated the CS Signal or the RW4 signal or the SEVEN signal. We have also partially enabled the I/O buffer control gate.

I/O READ

Now, if this is a I/O READ operation, the computer will lower the I/O READ line. This line is presented to four gates. First i t will fully enable the I/O buffer control gate IC16-13 which will cause the input buffer IC43 to turn off and then 'the output buffer IC44 to turn on. Second i t is combined with RW4 in IC31a. Third, ,it will combine with CS in IC18a.

If the RW4 signal was active, I/O READ combines with RW4 to generate the RE4 signal at the output of IC31a. This signal enables octal buffer IC42 onto the I/O bus allowing the ,computer to read the data in the D Latches IC41, the drive attribute bits, and the two status signals from the

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DOUBLE DENSITY SYSTEM MANUAL CHAPTER 4: THEORY OF OPER~TION

controller IC29.

If the CS signal was active, I/O READ combines with CS to form RE at the output of IC18a, which when generated, will gate the controller register, selected by the lower two address lines, onto the I/O data bus for the computer to read.

The I/O READ signal is also presented to IC19a, to be gated with the SEVEN signal, but this is in the Wait logic and will be discussed later.

Now, if this is WRITE line. This with RW4 in IC31b.

I/O WRITE

an I/O WRITE operation, the computer will lower the I/O line is presented to three gates. First, it is combined

Second, it is combined with CS in IC18b.

If the RW4 signal was active, I/O WRITE combines to form WE4 at the output of IC31b. This signal provides the strobe pulse to the Device Select, Side Select, and Interrupt Enable D type Latch IC41. It also conditionally enables the Drive Change signal(DR CHG) at IC16c. If Data bit 4 is low true at the time, the DR CHG signal is generated at the output of IC16c.

If the CS line was active, I/O Write combines to form WE at the output of IC18b. This signal enables the Controller register, selected by the lower two address lines, to be written into by the computer.

The I/O WRITE signal is also presented to IC19a, to be gated with the SEVEN signal. This is in the Wait circuit and will be discussed later.

I/O BUFFERS

The computer data interface to the controller is through three Octal buffer IC's 42, 43, 44. The controller's internal data bus is a low true bidirectional bus. When the board is not being accessed, the normal state of the internal bus is recieve. This normal state only changes to transmit when the computer has presented the proper port address and the I/O READ signal is active low. Since the computer I/O input bus is inverted, the Octal buffer IC44 is noninverting so that the controllers internal low true bus is gated to the computers low true I/O input bus. Octal buffer IC42 converts the high true data on its inputs to low true data for the controllers low true data bus.

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-DOUBLE DENSITY SYSTEM MANUAL CHAPTER 4: THEORY OF OPERATION