General
Please refer to Pictorial 2-12 while you read the following para-graphs.
As stated in the discussions on the 8085 and the 8088, the address and data lines of these CPUs are multiplexed onto the same bus. That is, first the address is present on the bus, then the data. A control line called the address line ena-ble, or ALE, separates these signals and sends them to their appropriate latches.
Under normal operation, the CPU selection logic enables either the 8085 CPU or the 8088 CPU. Although the address/
data lines of these processors are connected in parallel, the bus of the disabled processor is 3-stated, and so does not interfere with the active CPU.
Since the 8085 and 8088 timing diagrams are similar, the 8088 waveforms may be used for the following description.
ONE BUS CYCLE
'z
CLK A19/S8-6
A16/S3
ADDRESSOUT STATUS OUT ADDRESS OUT 1 5 8
ADDRESS
AD/-ADD OUT DATA
ALE
10/M LOW MEMORY, H I GH= I/O
WR OR RD
Pictorial 2-12
iAPX88 Basic Machine Cycle
Address Latches
At the beginning of clock cycle T1, the 8088 asserts the 88ALE line at U211 pin 25. This signal couples through the OR gate at U221 pin 1 to pin 11 of U197 and U196, which are two 3-state, octal, D-type latches.
A short time later, the 8088 places address data on the ad-dress lines. The lower eight bits, ADO-AD7, go to U197; and the upper eight bits, PA8-PA15, go to U196. These latches are transparent as long as the ALE line is high; that is, the output logic levels are the same as the input logic levels. At the end of T1, ALE goes low to latch the outputs with the address.
The line going to pin 1 of U197 and U196 provides S-100 compatibility, allowing another card to take control of the bus.
If an external processor or DMA device were plugged into one of the S-100 slots, and it was to take control of the Com-puter, it would assert ADSB* low. This would 3-state U197 and U198, thus blocking off the 8085 and 8088.
CIRCUIT DESCRIPTION
Data Latches
If the CPU is writing data, either to memory or to an output port, it asserts the WR line at U211 pin 29. This signal is inverted by U220 pin 12 to form the CPUWR control signal.
CPUWR connects to U198 pin 11 and holds this latch transpa-rent as long as it is high.
During time T3, the CPU places the data on bus lines ADO-AD7, which couple through U198 to its outputs. At time T4, CPUWR goes low to latch this data onto DOO-DO7. From here, the data is sent to the location pointed to by the address on U197 and U196.
U198 pin 1 is the inverted version of DODSB* from the S-100 bus. This signal functions in the same manner as ADSB*.
If the CPU is reading data, either from memory or an input port, its timing is the same as when it writes data. However, this time it asserts the RD line at pin 32. This control line is inverted by U220 pin 4 to form RD.
Control line RD connects to U235 pin 11. The other two inputs to U235, 8259ACS and 8259ACM, are from the interrupt cir-cuits. These two inputs go high when an interrupt occurs.
Since RD is high, pin 1 of U217 is low, and this 3-state octal buffer passes the data on bus lines DIO-DI7 to ADO-AD7. At time T3, the CPU assumes that the data is stable and loads
it into its accumulator.
Extended Addressing
The extended addressing circuits; U193, U212, and U213;
maintain S-100 compatibility by making it possible for the CPU to address up to 16 Mbytes of memory.
When the 8088 is active, U193 pin 1 is high and couples PA16-PA19 to pins 3, 4, 7, and 8 of U213. When ALE asserts at U213 pin 11, these address values are coupled over to A16-A19. Lines A20-A23 are logic 0 because the outputs of U212 have not changed from their cleared condition. In this case, the 8088 is operating normally and can directly address its natural 1-M range.
To access the address space above 1M, the CPU asserts Hl-ADCS from the I/O port decoder (U159 on MB2). Then CPUWR is asserted causing U221 pin 6 to go low. Finally, the extended address is placed on lines AD4-AD7 at U212.
(Lines ADO-AD3 are blocked by U193.)
At the end of that cycle, the CPUWR line goes high and latches AD4-AD7 onto the outputs of U212.
At the beginning of the next machine cycle, when ALE again asserts, the outputs of U212 latch into U213. For example, if U213-12 is logic 1 and pins 15, 16, and 19 are 0, the CPU is in the 1- to 2-M range.
These circuits work the same way if the 8085 is the active CPU. The only difference is that 88SELD at U193 is low so that the lower four bits of U212 couples directly to U213. This allows the 8085 to address memory between 64K and 1M.
Note, however, that once the CPU jumps to these higher ranges it cannot return unless there is a program there to tell it to return. This is because U212 and U213 are latches and can only be changed by software that writes to the high-address port (or through a hard reset). One way around this is to preload a program in higher memory by using direct mem-ory access.