---A.1 THE 2422 ACCESSIBLE REGISTERS
The 2422 Floppy Disk Controller contains nine accessible registers for controlling disk operations. They are addressed as six 1/0 ports or, if the memory map decoding ROM has been installed, six memory locations. Five of these registers are internal to the FD1791: the Status register (read-,only) , the Command register (wri te-only), the Track register, the Sector register, and the Data register. Four
rE~gisters are external: Control registers 1 and 2 (write-only) and status Registers 1 and 2 (read-only). In addition, the 2422 contains a write-only register for bank selection. The registers are addressed as follows:
========================================================
Address Register
======================================================-1/0 Memory* Read Write
30 FFF8 Status Command
31 FFF9 Track Track
32 FFFA Sector Sector
33 FFFB Data Data
34 FFFC Status 1 Control 1
04 FFFD Status 2 Control 2
40 Bank Select
* Memory Map address decoding ROM must be installed.
~- ~-
--Table A-1 2422 Register Addressing
The FD1793 Data Sheet included with this manual gives bit descriptions for each of the 1793's internal registers. Descriptions of the external registers follow.
A.1.1 CONTROL REGISTER 1
Control Register 1 sets the basic conditions for drive operations. All bits are reset when the 2422 is reset.
Table A-2 Control Register 1
=========================================================================
: BIT 7 : BIT 6 : BIT 5 : BIT 4 : BIT 3 : BIT 2 : BIT 1 : BIT
°
:========:========:========:========:========:========:========:========:
: AUTO : DDEN : MOTOR MINI DS4 DS3 DS2 DS1 : WAIT : ON
=========================================================================
Bit Definitions:
Bit 7
Bit 6
Bit 5
Bit 4
When set to 1, bit 7 enables the Auto Wait circuitry. Once enabled, the Auto Wait circuitry places the CPU in a wait state whenever it attempts a data transfer with the 2422 when the DRQ (Data Request) line is low. The CPU will remain in a wait state until DRQ goes high. When reset, the Auto Wait bit disables the Auto Wait circuitry. Besides being reset when the 2422 is reset, the Auto Wait bit is reset when INTRQ goes active, indicating that the 1793 has finished executing a command.
When set to 1, bit 6 conditions the 2422 for reading and writing double-density formatted diskettes. When reset, bit 6 conditions the 2422 for single-density operation.
Bit 5 controls the state of the MOTOR ON* signal. Set to 1, it turns on the spindle motors of all drives receiving the MOTOR ON* signal. When reset, it turns the motors off.
Set to 0, bit 4 conditions the 2422 for operation with mini drives. Reset to 1, it conditions the 2422 for operation with 8" drives.
Bits 3-0 These bits control the state of the Drive Select lines to the individual drives. Set to 1, a Drive Select bit activates the Drive Select line to the corresponding drive, selecting the drive for disk operations. Only one drive should be selected at a time.
A.1.2 STATUS REGISTER 1
Table A-3 status Register 1
=========================================================================
: BIT 7 : BIT 6 : BIT 5 : BIT 4 : BIT 3 : BIT 2 : BIT 1 : BIT 0
:========:========:========:========:========:========:========:========:
DRQ AUTO BOOT
HLD DS4 DS3 DS2 DS1 : INTRQ ::========================================================================
Bit Definitions:
Bit 7
Bit 6
Bit 5
Bit 4-1
Bit 0
Bit 7 reflects the state of the DRQ (Data Request) signal from the 1793. During disk writes, a 1 in bit 7 indicates that the 1793's data register is empty and can accept a new byte to be written to disk. During disk reads, it indicates the 1793's data register holds a data byte to be read by the CPU. A 0 in bit 7 indicates the data register is not ready for data transfer with the CPU.
Bit 6 is used by the CCS firmware during cold-start initialization to determine whether CP/M or the monitor is to be entered. If the shorting plug is placed on the AUTO BOOT pins 1 and 2~ bit 6 is set to 0, causing the cold-start initialization routine to turn control over to the bootstrap loader. If the AUTO BOOT pins are open, bit 6 is set to 1, causing the cold-start initialization routine to turn control over to the monitor executive.
Bit 5 reflects the state of the HLD* signal from the 1793. A 1 in bit 5 indicates that the Read/Write Head of the currently-selected drive is loaded.
When a Drive Select bit is set to 1, its corresponding drive has been selected for disk operations.
Bit 0 reflects the state of the INTRQ signal from the 1793.
This signal goes high when the 1793 has finished executing the current command in the command register and is awaiting a new command.
A.1.3 CONTROL REGISTER 2
This secondary control register sets less frequently used conditions for drive operations. All bits are reset on power-on, reset, or external clear.
Table A-4 Control Register 2
~====================================~===================================
: BIT 7 : BIT 6 : BIT 5 : BIT 4 : BIT 3 : BIT 2 : BIT 1 : BIT
°
=========:========:========:========:========1========1========1========:
BOOT : SIDE : don't: FAST don't: REMOTE: don't: don't : SELECT: care SEEK care: EJECT care I care
---
---~---
---Bit Definitions:
Bit 7
Bit 6
Bit 4
Bit 2
If pins 2 and 3 of the ROM EN jumper have been shorted, this bit enables/disables the monitor/bootstrap loader firmware.
Set to 1, it enables the firmware; reset to 0, it disables the firmware.
This bit controls the state of the SIDE SELECT_signal to the currently-selected two-sided drive. Set to 0, bit 6 selects side 1 of a two-sided diskette for a read or write. Reset to 1, bit 6 selects side
°
of a two-sided diskette.If pins and 2 of the FAST SEEK jumper are shorted, bit 4 enables/disables the fast seek mode for voice-coil drives.
Set to 1, it enables the fast seek mode; reset to 0, it disables the fast seek mode.
If pins 1 and 2 of jumper D have been shorted, bit 2 controls the state of the PerSci REMOTE EJECT signal. Set to 1, bit 2 causes the diskette in the currently-selected PerSci drive to be ejected.
A.1.4 STATUS REGISTER 2
Table A-5 Status Register 2
---: BIT 7 : BIT 6 I BIT 5 : BIT 4 : BIT 3 I BIT 2 I BIT 1 : BIT
°
1========1========1========1========1========1========1========1========1
: DRQ : TWO- DDEN: INDEX : SIDE : WPRT MINI: TK 00
I SIDED I SELECT :
=========================================================================
Bit Definitions:
Bit 7 Bit 7 reflects the state of the DRQ signal from the 1793.
During disk writes, a 1 in bit 7 indicates that the 1793's data register requires a new byte. During disk reads, a 1 in bit 7 indicates that the 1793's data register holds a data byte to be read by the CPU. A
°
in bit 7 indicates that the 1793's register is not ready for data transfer.Bi.t 6
Blt 5
Bit 4
Bit 3
Bit 2
B:it 1
Bit 6 reflects the state of the signal TWO-SIDED* from the currently-sel,ected, double-sided 8" dri ve. A 0 in bi t 6 indicates a two-sided diskette is in the drive.
A in bit 5 indicates that the 2422 has been conditioned to read or write double-density formatted diskettes. A 0 indicates the 2422 has been conditioned for single-density diskettes.
Bit 4 reflects the state of the INDEX* signal from the currently-selected drive. It is set to 0 for a minimum of 10 usecs. when the drive detects the index hole on the diskette.
Bit 3 reflects the state of Bit 6 in Control Register 2, thus indicating which side of a double-sided diskette is selected.
A 1 indicates side 0; a 0 indicates side 1.
Bit 2 reflects the state of the WPRT* signal from the currently-selected drive. (On some drives write protect detection circuitry is an optional feature.) A 0 in bit 2 indicates a write-protected diskette is in the currently selected drive.
A 1 in bit 1 indicates that operation with a 5.25" drive.
conditioned for an 8" drive.
the 2422 is conditioned for A 0 indicates that the 2422 is
Bit 0 Track 00. This bit indicates whether the currently selected drive is a 5.25" or 8" drive. When the head is positioned over Track 00, bit 0 is low for a 5.25" drive and high for an 8" drive.
A.1.5 Bank Select Register
Table A-6 Bank Select Register
::::=:::::::=:::::::::::::::::::::::=:::::::=:=:=:::::====================
: BIT 7 : BIT 6 : BIT 5 : BIT 4 : BIT 3 : BIT 2 : BIT 1 : BIT 0
,---~--- ---
.--~---
---: BANK 7 : BANK 6 : BANK 5 : BANK 4 : BANK 3 : BANK 2 : BANK 1 : BANK 0 : : SELECT : SELECT : SELECT : SELECT : SELECT : SELECT : SELECT : SELECT :
---,---
---The bank the 2422 is assigned to is selected when its bit is set to and is deselected when its bit is reset to O. The remaining seven bits are Don't Care bits. On reset, all eight bits are set to O. Note that if pins 1 and 2 of the ROM ENABLE jumper are shorted, any byte output to the Bank Select Port disables the bootstrap loader and monitor firmware.