is ity

r----+----,

I ^BUG 5 I

L ____

+-___

^J

BOGUS

Brown anivecsity Graphics System'

L8VELO Extended Machine

The Brown Univecsity Graphics Project

Division of A.pplied Mathematics

Box F

Brown University

Providence, Rhode Island 02912

Updated: June 25, 1974

Printed: September 15, 1976

lThis research is being supported by the National Scie nce Foundation Gr ant GJ- 29401 X, the off ice of Naval Resear ch, ContI:act N00014-67-A-0 191-002J, and the Brow n University Division of Applied Mathematics; Principal Investigato[ Andries van Dam.

1 Introduction ..... . ... . ' ... 1 2 The

2. 1

LEVELl Routine and Its Stack Frame.

LEVEL1 vs. the Bare Machine •••

Non-privileged State •••••••

2. 1. 1 2.1 .2 2.1 .3

WAIT Sta te ... ..

Extended Instructions • • • • • 2.2 The Programmer's Data ••••••••••••

2.2.1 sta tic Da ta 2.2.2 Automatic Data 2.2.3 Controlled Data. •

.

^,.

... .

· .

• 2.3 The Stack Frame ••••••••

2.4 Subroutine Linkage Instruct ions.

2.5 Types of Routines . . . • 2.5.1 Parallel Routines. Subroutines ... .

· .

••

..

. ^.

•

•

.. ..

. .

. _.. ^.

•

•

· . . ..

^..

... . ...

• 2 ... .. ... 2 ... 2 • 2

• ... 2

.. ...

^]

,.

... . ...

^.3

· ^.

_.. . . . 4 .3

· ^· · ^· · · ^. · · · · · ^. · ·

^.4

· · · · ^· · ^· · ^{· .} · · ·

⁵

· · · · ·

^.6

· ^·

^•

· ·

^•

^{· ·} ·

^.6

· · . ·

^•

· · ·

^{• •}

· ·

^.7

2.5. 2 2.5.3 2. 5. 4

Immediate Routines.

Registers at Entry

.

_to

^{. .} ·

a Routine.

.

^•

...

•

·

^•

· · ^· · ^· · ^· ·

^.8

3 Events and Their Routines .••..

Events . . . . 3. 1

3.2 Dispatching of Parallel Routines. •

· .

3.3 LEVEL 1 Control of Routines and Events.

WAIT and POST.

. ^.. . ^{.. ..} . . . .

3 .3. 1

3. 3. 2 SIGNAL •••••••••••••••••••• • 4 Maintaining Controlled Data •••••

4.1 Getting Control led Storage.

4.7 Freeing Controlled Storage. • 5 Extended

5. 1

I/O ... ... .

. ^{.. .. .. .. ..}

^..

^..

^{.. ..}

Local I/O Units and the Channel ••

5.1.1 The Channel ·Program ••••• •• ••••

5.1.2 Starting a 5. 1.3 Other Local

Channel Program.

. ^{.. ..}

^..

I/O Facilities.

5.1.4 Handling of Parity Checks.

5.2 S/360 Communication.

5.3 The Interval Timer.

.. .

^'

...

. ^.. . .. .

S. 3.1 CPU and Running Time ••

5.3.2 Time Intervals • •

5.4 MET A 4 B Communica tions.

· .

6 Unit-Dependent CPCs.

6. 1 3461 Card Reader.

.. ... .

.. ...

6.2 Interval Timer . . . 6.3 4132 Keyboard/'Iypewriter •••

6.4 1444 Disk Storage uni't ... .

•

· ..

•

•

• ••

•

. _{· ·}

^.9

· ... .

... . ^.. ...

... . ... ...

10 10 13 13 B ..

.. .. . ^.. . ^.. . . ^.. · ... . .. .

14

•

· ... .

· ..

^•

· .

· .

15 15 15

16 16 ... 16

· .. ^{· ...}

¹⁷

... 1 8

· .

¹⁸ ₁₈

• • • • • .. • • • .. • • .. ... 1 9

. .

¹⁹

19 .. ... 1 9

..

...

• .21 .. • 21

• .. 21 21 22

6. 5 6.6

Control [lanel . Null META ^{4B ••}

7 A P pe nd i x I : LEVELO-Defined 7.1 Interval Timer Events.

7. 2 META 4B Events ••••••••

Events.

• • 7.3 Null ME11A 4 B Evehts . . ....... • ..

7.4 Other Local I/O Unit Events •••

7.4.1 3461 Card Reader •••••••••

7.4.2 4132 Key board/Typel/riter.

7.4.3 1444 DiSK Storage Unit ••••••

7.4.4 Control Panel •••••

.. .. .. ..

Events ... ..

7. 5 s vc

7.6 Program Inte.l:rupt Events.

Program Manipulation Events.

7.7

7. 8 Event Trap •••••••••••••••••••••

. . .. ..

•

•

. . ^{.. ...}

•

•

• •

• •

. .

•

.. ...

· ..

• •• 23

23 . 25 .25

.. ... .. 25

.. .. .. .. .. .. .. .. .. .. 2 5 .. ... .. 26

.... .. ... ..

26 26

...

26

• •

...

.. .. ' ... .. 27

• • •• 27 27 .. ... .. 27

.. ... ..

27

8 Appendix II LEVELO Lower Memory Layout ... 28

9 A P pe od i x I II lEVELl Progcam Inter['upts •• ,. . . . 30

10 Appendix IV: Extended Instruction op Codes ••••••••••••••••••• 31 11 lIppendix 11. 1 V: M4ALIB Macros ... 11.2 11. 3 11.4 11. 5 EV EN T • ... • ... AUTOjENDAU'fO •• RETCODE. C PC ... LEVF:LO.

. ^{.. .. ..} . . .. .. _. . .. . .. . ..

^,.

. ^{... .} . .. . ^{.. .. ..} ... . ^. . . . . . . ^{. . .} . . . . . . . . ^.. . . . . ^{. .} .

-ii-

.. ... .

^.32 ..

...

• ... 32

• .. .... • ' ... .. 32

· ...

... ] J

· ... .

^{•• 33}

· ... · ... ... .

^{• • 34}

This publication describes th~ LEVELO ExtEnded Machine, a component of the Bro~n Operati.ng Graphics University System, runniug on the BUGS 11ETA 4A pl:ocessol:. LEV.ELO provides tile BUGS use r: wi·th facilities beyond those inherent in the hardware/firmware. A thorough knowledge of the principles of Opera tion of the MET A '. A is assumed.

LBVRLO i s a softwace package designed to run on the META 4A and provide the BUGS user with facilities making up an e xtended machine. These facilities alleviate some of the deudgeey of coding on a bare machine and assume responsibility foe many maclline f unctions. feeeing tile user to worry about th8 operation of [lUGS (referred to as the "system") a t a higher level. LEV ELO assumes the presence of another level of operating s ystem, rUTlning as a "LEVELl" above i t. Suc h a LllVEL l (loes exist on BUGS, and is called the G.raphics Monitor System (GMS) , or, to close friends, "Oue Fearless Leader" . III ttds pub] ication,

howevee, it will be .refecced to as LEVELl tor gene rality.

The reader is assumed to have a thorough knowledge of the META 4A and BUGS in genecal. In pacticular, however, ae will use only those "normal" i ns tcuctiollS not concecned with machine status , interrupt handling, I/O, etc. LEV.ELO is respons ible for handl ing those port i ons of t he machine. ~hus i t is necessary for the reader to realize that much of what be reads in the META 4A Principles of Operation will not directl y concern him.

- 1-

1\ LEVELl r-outine ruoning OIl LEVELO must tollow somewhat differ-ent conventions from one r-unning stand-alone on the HETA

4&. These conventions a~e necessar-y for- two reasons. fir-st of all, they allow LEVELO to maintain control over t he status of tile system, and secondly, they pr-ol/id€ a higher level of system organization for the LEVELl pr-ogr-ammer-.

2.1.1 NON-PRIVILEGED STATE

The LEVELl r-cutine r-uns at all times with the Pril/ilege bit in the MSR ofL This prevents him f rom pertor-ming local I/O and 5/360 operations wi thout usi ng the facilities rrovided

by LEI/ELO. Specifically, he cannot exec ute the following instructions: 5IOR, 510, llST, liST, EXCC, TilB, and 55. It is consider-ed invalid for the LEVEL l system ever- to set the Privilege bit on.

2. 1. 2 II 1\ IT 5Tll TE

In addition to nevel: set the control of the of this bi t.

the Privilege Wait bit in state of the

2. 1. 3 EXTENDED INSTRUC'IIONS

bit, the l EVELl pl:ogram must the M5R. LEVELO assumes all system, including the setting

Because of the above re strictions and for the iocr-eased flexibility of LEVELl, LEVELO provides a set of "Extended Machine Instr-~ctions". These instructions, which ar-e coded by the progr-dmmer as if they were real META 4A

instructions, pr-ovided added features for LEVEL l, such as memor-y management,extended I/O, et c. These instructi ons, of

which ther:e at: _ some fifteen, will be explain",d in the cour:se of this publication.

Since computing is concet:ned with the manipulation of data, str:ict conventions concerning types of data are made by LEVELO. There are specifically three types of data with which the programmer can concern himself: static. automatic. aud controlled.

2.2.1 S'l' A TIC D AT A

Static data is data that is assembled/compiled into a routine and is prese·nt there when the routine is loaded.

This data includes the iustrnctions of the progeam itself.

plus any pre-initialized va riables DCed within the routine proper. The term "static" may be misleading in that i t is not assumed that static data will mmain unchanged throughout the execution of a program; i t is certainly possible for a programmer to DC an initial value for a variable and then change it later. The ter:m static simply implies that the data was defined before execution of the r:outine was begun.

2.2.2 AU'l'O[1A'l'IC DATA

Automatic data' is the teem applied to vaeiable space which is allocated prioe to the execution of a routine and freed when tha t r:outine com pletes. This data cannot be initialized at assen.bly!compile time, because the storage does not exist at this point. The data is local to the routine owning the automatic storage and disappear:s when that routine completes. It is this type of data that is special ly treated by LEVELO.

- ) -

2.2.3 CONTROLLED DATA

Controlled data is data which is maintained in storage space obtained by a routine and present until e xclicitly

released. Extended instructions are provided to maintain this controlled storage. Most programmers are probably familiar with this type of storage from experiellce wi th IBN operating System/360 or similar systems, with thei r GETtHlIN and FREEflAIN SVcs.

As was me ntioned above, automatic storage is onp. special feature of LEVELO. In order to maintain this automatic storage across normal occurences such as subroutine calling and the execution of interrupt ha ndle rs and the like , LEV ELO maintains a number of "stack frames" in the META 4A. 1\ stack frame is a logically infinite piece of storage in which is maintained a serl.es of automat ic storage sections .for each routine in the dynamic seguence of execution. Each routine need only be concerned with the section of the s tack frame belonging to him. This section has the following format:

SFP I V

r-· ---, o

^{Iprevious poillterl}

r---~

2 I next pointer I Ir---'/

4 I I

sa ve area

I I

l - - - j

221 I

all toma tic storage

L _ _ _ _ __ _ ___ _ _ - J

pl:e vious pointel:: this halfwol:d contains the address of the stack frame sectioD of the routine executi ng dynamically prior: to this routine.

next pointer: this pointer dynamic link of stack use to the programmer.

i s used by L EVELO to maintain the frame sections dnd is of no direct

(vj;<) I.'Y t,<-< Jb,.>_ ".~_,)

save area: these 15 halfwords are used to store the routine ' s MSR tlll:ough register 14 at auy time his execlltion is delayed due to an actual machinE interrupt or to a s ubroutine call.

i}' !,...J""r,~

automatic storage: This space is the ac·tual automatic st~rage

requested by the routine. It can vary ill size f.rom 1 to n halfwords; this size is de termined by the extended insteuct ion EN T, wh ic h nltlst be the

ii£§i

i nstr uction ^{0 f} every routine that either saves the registers of the previous routine or requires automatic storage or both.

ENTer routine ENT RI

The immediate halfword of t his RI-format extended instruction s pgcifies the size, in bytes, of the automatic storage required by the routine. The s ize is rounded up to the next higher halfword, if necessary, a nd used to determine the size of the automatic storage shown in the diagram above. This instruction must be the first executed instructioll of evgey routine in which it appears.

Once the ENT instruction i s performed, the caller's registers

o

^{through 14} are saved in the calle r' s savearea, and the Stack Prame Pointer (SFPl. register 15, is set to pcint a t the stack frame section for the EN'fered I:Gutine . This registel: may ·be used as a base for instl:uctions accessing data out of the stack frame, but shou.ld not be modified in any way by the

I:outine. Tts contents al:e maintained entil:ely by LEVELO .

Once a routine has completed execution, i t must cetuen conteol to the I:outine dynarnica 11y pl:evious to it. This is done by executing the RET extended ins·tl:uction:

RETurn from I:outine BET Rl1

This instcllctioll. which has no operands, causes the stack frame section allocated to the routine to be fl:eed up, and contl:ol to be I:etul:ned to the interrupted point of the

pre vious rou·tine. l'he SFP will l:e backed up so as to be

-5-

.~

cOLrect fOL the p.rior Loutine and registeLs 0 thLough 14 restored ELom i ts savear ea. I f the Leturning Lout.ine desires to modify the registers of the previous routine, an actioD which is entirely valid in certain caSES, he may do so by picking up the previous pointer and using i t as a base to address the pce vious r:egist el:s. If the ret ucni ng 'coutine i s re-enteced, it.s autowatic storage will have been in no way presecved. The contents of automat ic stocage are always undefined at the start of a cout ine .

At this point in time we can begin to ffiake a distinction between various types of coutines, namely pacallel coutines, subcoutines, and immediate routines.

2.5.1 PII!lALLKL ROUTINES

A pacallel coutine i s one Which can cun simultaneously with and independently of any and all other coutines. LF.V ELO has the capability to run an arbit cacy numbec of parallel coutines simultaneously within the s ystem. Each paLallel contine is given control and allowed to execute until some event occucs that LEV ELO decides should cause another pacallel coutine to gain cont rol. Each paLallel routine has its own "infinite" stack fLame whicb remains in existence until that Loutine returns. At the front of that st ack frame i s a section of s toLage known as the "stack f rame header", which has the following fCLmat~

r---r--- -, o

^I pa La 11 el '1 ue ue I

I---+---- --j

2 I priocityI I I I I I I I j

t---+---;

4 I stack frame si ze I

I---+---~

6 I _{L ___ _____} SFP save l

~ _______ J

parallel gueue: this pointeL is used by LEVELO t o maintain a queue of the stack frames of each of the pacallel routines currently Lunning on the system. The head of this queue is in memory loea tion X '60 '.

priority: This byte contains the priority assigned to this parallel event. The priori ty is used by LEVELO to decide which parallel e vent shcullt be given control each time s uch a decision must bE made. See Section

3. 2.

stack frame size: This halfword size ~stimatio,Il made by the

3. 1. JV!":

contains the stacK frame prog rammer. See Section

SPP save: Whenever the parallel routine is not executing.

i t s c urrent SFP is saved in this halfword.

The previous pointer in the stack frame section of a parallel event is zero because there is no dynamically previous routine. Each pa·ral lel event is considered an entity in itself and control is ne ve r passed betl,een them under programmer request.

. h.,...v,...~ ?

Al so associatedl

,

with the entry into such a routine is some pre-determined 'gata called "status". This data is stored into the first fe bytes of the routine's automatic storage by LEVE10 before that routine is placed on the queue. The programmer must i nclude this space in his automatic storage request in the ENT instruction. This data will be explained in greater detail later. (l) ~rl

2.5.2 SUBROUTINES

A subrout jne .is a routine which is expl icitly invoked by another routine. Although the su broutine is logically a separate routine with i ts own automa tic storage. LEV ELO considers i t to be an extension of the invoking coutine.

It gets its 'stack f.rame sectien oot of the stack £.rame of the i nvoking routille. and i t runs with the priority of the originally entered parallel routine.

The programmer exercises expl icit control o ver t he execution of subroutines; in order to invoke one he must

l oad the return address into register 14 and branch to the ENT instruction of the subroutine , via:

BAl R 14,subroutine or, if the subroutine is external:

11 BALR

Rx, V (sub routine) R14,Rx

-7-

i'

When t he subroutine i s e ntered, the contents of the registers will be ide ntical to what they were in the invoking routine, e xcept of course for the SFP. It is not necessaL¥ tOL the s ubroutine to l:estore an Y Legisters before exiting with a RET inst~uction; this is taken care of byLEVELO with tbe save areas.

A subl:out ine itsel f may call other subroutines, down to any level. If a subroutine desires t o modify t he registers of the invoker, he may do EO as e xplained io section 2.3, by using the previous pointer as d baSE tor the invoker'S stack frame section. A typical case of this i s fOI:

implementing I:etllrn cones.

2.5.3 IMMEDInTE ROUTINES

o immeniate Loutine, unli ke a parallel one , cannot l:un simultalleousl y with otller routines. The purpose of the immediate routine is to perf orm system lIlilintainence f unctions, such as the handling of I/O interrapts, as quickl y and with as little ovel:head as possible. To accomplish this, a immediate routine must:

1) Run disabled, i. e. , with the I/O and 5/360 intel:rupt masks in the MSR off. This ensures that the e xecution of the routine will not be interrupted by any extel:nal unit.

2) Not issue a ny another paralle l These restrictiollS

instructions.

extended routine will be

instl:uctions which would cause to gain control of the system.

descri bed under tbe ilppropriate

An immediate l:outine, however , may cal l s ubl:uutines and may cause ot~e£ ' immediate routines to gain contl:ol . Any subroutine called must dlso foLlow the above conventions.

An immediate routine and al l its subroutines, because they do not run in paral le l with othe l: routines, do not have their own stack frame. Instead, they run in the stack frame of the paralle l routine that was e xecuting at the time the immediate routine was invoked.

2. 5.4 REGISTERS AT ENTRY TO I ROUTINE

The following table desc~ibes the s tatus of the registers UpOll e ntry to a parall el or immediate routine:

MSR: Condition Code and Flag zero; Arithmetic Overflow and stack (lverflow/Onderflc~ disabled; iJlterrupt masks as described above. Parity i nterrupts are always enabl ed, and the Parity interrupt mask bi t in the r1S11 should not be altered.

PC: Set appropriately.

82 R3: Identica l to what they were when the formerl y executing routine was interrupted. This is es~ecially

useful for SVC handling rOllti.nes, which are pass ed parameters in these registers.

84 - R 14: Undefined . SFP: Set appropriatel y.

Now that t he various types of roudnes a vai lable on LllVELO have been discussed, i t i s time to describe how indiv~dual rout~nes

are invoked. The siwplest case is that of subroutines, which are explici tly invoked by the programmer as described in section 2.5.2. I t i s parallel and immediate rout ines that th~s section deals with.

Till e ve nt in DUGS is defined as the occurence of some sort of syst e m interrupt that s hould delay the execut~on of the curJ:ent routine and s tart uF a nother. Events are s uch t hings as I/O interJ:llpts , SVC calls , Program Checks, etc. LEVELO presumes that the LEVELl system will havE a routi ne which s hould be eXEcuted whe n each of these e vents occurs , and the refore nlus t invoke the peoper routine at the proper time.

In order to do this, LEVELO needs an EVent List (EVL) , which i s a l ist of entries , each one specifying an e ve nt and the routine to be invoked when it occurs . Each event e ntry has the following format:

r--- T - - --' o

I EVL link I

\---+---- -1 2 I event name I

t- - - - ---+ - -- ---l

4 Ipriorityl flags I r---+---~---i 6 I rout ine entry I /---+---1 8 ls tack frame si zel

l _______ - i _ _ _ _ J

EVL link: This i s the address of the next entry in t he EVL.

event name: This i s the 16-bit naDie assigned to the event . Many eve nts have names pre-assigned by lEVELO so that an effective communication with LEV Fl. l can te set up. Other event names can be assigned by LEVELl. The first hex digi t of the name is called the event "type", and is used in searching the EVL.

priority: This is the 8-bit prio.rity assigned to the event routine if i t is parallel. It i s used in determining which parallE!l routine to run, as described below.

flags: This byte contains flags describing the event routine:

bit 0: If zero" this routine is routine is parallel. The immediate routines.

immediate. If one, the priority is ignored for

bit 1: If on, no rou ti ne dynamically

the event is is invoked. by the LE VE L 1

ignored when i t occurs and This bit may be al tered syste m.

routine e ntry: This is the address of the routine i tself.

The first instruction must be an ENT specifying the amount of automatic storage desired by the programmer. stack f1:ame si ze: This halfword i s only used for paral lel

routines. As was mentioned previously, the stack frame is a logically infinite ,:i ece of storage. In actuality, i t i s composed of one or m01:e stack i1:ame extensions. This halfword should contain an e stimation of the total amount of s tack frame space needed. so that the f irst extension wi l l hopefully be the only one. This c uts down on LEVELO overhead and the fragmentation of memory.

In orde r to l ocate the event entry for an e vent when i t occurs, LEVELO uses a tabl e of EVL "heads"² • The1:e are s ixteen halfwonl e'itlnt heads, located in memory locations 70 through 8E. Each head is .Ised to point to the EVL for t he corresponding event type. I t i s up to the LEVEL1 system to set up the event hedd table in its initialization code. Th sixt een event types are:

o

^{Interval Timer e vents}

1 META 4 B events

2 All othe r local I/O unit e ve nts 3 5/360 events

4 )

5 )

6 )

7

>

events for LEVEL1 use

8 )

9 )

A )

2yig~ section 8 for the location of these l ists.

- 11 -

B )

C SVC events

D Program Interrupt e vents 8 Program Manipulation events F Event trap

The following steps are taken when au event occurs:

1) LEVELO builds the appropriate event name and extracts the first hex digit as the event type.

2) The event type is used to pick au BVI head from the above table, and the EVL is searched for an entry containing the na me.

3) If none is found, the fo uI:th hex digit of the event nallle is zeroed and t he list is sea rched again. This allows generic classes of events.

4 and '» If st i 11 are made, \~ith the al so zeroed.

no event entry is found, two more searches third and second hex digits, respectively,

6) Finally, if the above searches were unsuccessful, a check is made of e vent type F, the event trap , to see if any entry e xists in tha t EVL, regardless of namE'.

I t i s event e ntry entry

presumed that one of the above searches produces entry which can be used to invoke a routine. If was produced, the e vent is ignored and discarded. If was found, the follcwing ac tions occur:

an no

all

parallel event:

specified in the priority the que ue ~f

A new stack the en try.

and t he ira me stack frallles.

frame is created with the size The header is initialized with

si ze and placed at the head of

immediate event: The routine is space in t he current stack ENT instruction.

entered after allocating it frame in accordance with i ts

No action is taken of course, event entry.

if tho ignore flag is Oil in the

There

t ha t

are cectain conditions under the current parallel couline another one given control. Whenever

"dispatcher" is executed. It performs

which L£V£10 d~tarmines

should be delayed and this occurs, the 1EV £10 t.he following seacch:

1) A scan of the parallel queue is made for t.he highest priocity runnable parallel routine. A routine is not r unnable if i t has gone into "ait state (s ee section 3.3. 1) . If two or more have the highest Friority, the last one on the queue is pic ked.

2) If all rout.ines are ill wait. state, the fi.rst one is picked.

Once a routine is picked, it is given control by ~oadlng its current SFP from the stack frame header and picking up its registers from the save area. During its execution the address of the predecessor stack frame header all the event qU\Jue will be in memory location X'62'.

Ce rtain extended instructions LEVEL1 in controlling the occurence of events.

3.3.1 \~AIT hND POST

are provided by LEVELO t o assist execution of routilles and ehe

It is possible for a routine to put itself into wait state, i.e. a state where exec ution is suspended, pending notification or "posting" by another routine. Wait state i s controlled by the ,Iait Control Half word (I,Cll) , used as the communication link between the waiter and the poster.

WAIT on well WAIT HX

The second operand is a WCH, which is checked to see if bit

o

is on. If not, the SIP of the routine issuing the WAI T i s set into the WCH, and the routine is flagged as being in wait state by setting the Wait bit ill its lIsa. If bi t 0 i s

- 1 ) -

on, the WCH has already been posted and the routine i s allowed to continue. An immediate routine may QQ.l issue a WAIT.

POST wch POST fSS

The second ope~and is a WCR, which i s posted by tu~ning off the Wait bit in the MSB of the routine whose save area i t points to. The fi~st operand ~ddf~§§ is then moved into the WCR as a completion code and bit 0 is set on.

A typical use for I/O operat ioll to then WAITS on a handling routine.

the~e instruc tions i E for wai ting for an complete. h routine starts some I/O and WCH which is POSTed by the 1/0 interrupt

3.3. 2 SIGNAL

The SIGNAL extended instruction is p!:ovided to all ow LEVEL1 to force the i nvocation of an event routine.

SIGNAL event SIGN AL FSS

The second operand halfword i E the name of an event whose occurence is to be forced. The event may be paLallel or immediate and i ts !:outine will be invoked provided the EVL search i s successful and the ignore bit i s off. The first operand address points to the status to be placed in the beginning of the routine 's automatic storage. This status

must be in the following forma t:

r---~---,

Ilength I status I

L ______ ^~ _____________ J

o

2 n

An immediate routine cannot SIGNAL a parallel one.

A group of extended i nstruc tion a re provided so that LEVELl can easily mai ntain controlled storage. Contiguous areas of controlled storage are maintained in a l inked l i s t called ti,e Free ~lemory List (FML). The head of this list is in memory

location X' 64' .

GET controlled storage Register GET controlled s torage

GETR GET

ax

RR

The contents of i12 (GETR) or the second operalld halfword (GET) specifies t he arrount of ccntrolled storage desired. This size is rounded up to a multiple of four bytes and the storage is obtained from the E'ML. I ts address i s returned in R 1. If no contiguous piece of storage of thereguested size exists, a No

Free Memory Program interr upt occurs.

GET MAXimum controlled storage

The address of the largest contiguous piece storage is r et urned in Hl, and its le ngth If absol utely no storage lS available, Program interru~t occurs.

FREE contt:olled stot:age Register FREE controlled storage

GETl1 ^{A X} RR of free controlled i s returned in H2.

a No Free ^~lemot:y

FllEF.R PH EE

RIl RX The contents of Bl contains the address of an area of control led storage to be FHEEd, i . e . , Fut back on the FML.

The contents of 82 (FREER) or the seccnd operand halfword (FREE) contains the length of this area. I f the address is not e ven an Invalid FREE Program i nterrupt will occur.

- 15-

I

LEVELO provides a great many extended I/O fac i l i t ies to t.lle LEVEL1 programmer, both in terms of local I/O anti S/360 communications. These facilities provide a higher level o.f control over I/O and I/O interrupts, allowingLEvEL1 routines t.o be much s maller and logically simpler. In addit.ion, t hey eliminate all of the data codes a ssociated with QariOlls ulii ts and reduce al l data transfer to the EBCDIC code.

5. 1. 1 THE CHANNEL PROGBAM

LEVELO provides a logical "channel" which ^hclS the capability of executing multiple ope rations (LOCCs) at a unit via only one LEVEL1 instruction, EXCP, which initiates a chain of unit commands. These commands are known as Channe l Program Commands (CPCs ) and have t he following focmat:

r---.---r---,---- ,

Icommand Iflags I address I lengtll I

L -______ ~ ____ ~ _________ ~ ________ J

o

¹ 2 4 6

command: This byt e speci fies the partie ular. operation to

x1-

x2-

be perfo'rmed by this (PC at the unit. There are seven dif ferent command~:

Writ.e . Data specified

numbpr of

is trans ferred from the me mory dddress t.o the unit.. The lengt h s pecifies the bytes to transfer.

llead. Data is r ead from the unit into memory a t the l engtb determilles the address specified. The

number of bytes read.

x3- No Ope·cation. No operation is pe cf ormed a t the unit.

The address and l ength fields are ignored.

x4- Se"nse. The USH is read into the halfworu at the specified address. The length field is ignored.

x5- Sense with Reset. This CPC operates exactly as Sense with the addition that any pending inter rupt from the unit i s reset.

x6- Special. This CPC different units.

unit.

comllland has See the

special usage with eXFlanation of each

x7- Transfer in Channel. This CPC is not used to perform I/O at the unit, but rather to cause a branch so that the channel program may be continued at d

different memory location. The address field specifies from where the next CPC i s to be obtained; the length field is ignored.

flags: The only flag currently used i2 bit O. This bit i s checked atter comFlet i on of each epe except a Transter in Channel, and, if on, another epe is retrieved from

the D~I! three halfwords in memory. This feature, with Transfer in Char-nel, allows initiating controllable multiple operations at the unit with only one channel program.

address: This field specifies the ne mory address where data associated with the command is to be obtained or

stored.

length: This field gives a byte count for data transfer commands.

5. 1.2 S'rARTING A eHANN EL PR GRAM

EXecute Channel Program Exep FSS

The second operand address is the address of the first epc in the channel program. This program is initiated, i f possible, at the local unit Epecified by the 10~J-orcJ.er 4 bits of tile operand 1 EQQ£g§§.. The Condition Code is set as follows:

CO- C 1- C2 -

Unit busy or offline.

Channel progrdlO in progress.

Channel program completed immediately.

-17-

Once a channel program that caused Cl to be set is completed, an event ~ith a pre-defined name is signalled by LEVELO. This is to inform LEVEL l of i ts completion and any error conditions that occured, and to allo\~ LEVELl to perform any post-I/O housekeeping necessary. Appendix I l ists t hese event names and thei r associated status information.

5. 1.3 OTHER LOCAL I/O PACILITIES

In order to control I /O interrupts, i t is perfectly valid for LEVELl to manipulate the 1/0 mask bit in the ftSR and

the I/O unit mask in location 2E, within l imits. It is considered invalid for a immediate routine to e nable 1/0

illt err u pts.

In addition, LEVELl can never modify the DCB table or the UCBs for any unit. However, the third halfword of each .DCB is reserved for LEVELl use as a pointer to a DCa 8xt8Tlsion or whate ver. LEVELl may access this hal fword through t he UCB table and modify i t at wi l l .

5.1.4 HANDLING OF PARITY CH ECKS

When a Parity Check Control Pdnel interrupt occurs. LEV2LO goes into "har~' stopped state. The user can only recover by resetting the s ystem and re-IPLing.

Although S/360 liD logically be longs on LEVELO, it is currently s uppo.rted by a s ubroutine package which dyndmically

"hooks" i t se lf into LEVELO. See ~LL§Q _

t U;:ri .!!! ILQ.L

~!!Q.~Q!!.ti!!.~ Q~§££iEiio!!.§ for calling conventio·ns.

.1

The

Interval

Timer decrements

location

X'50' every 100

usec.

When location

X'50' goes to

ze

ro, it

causes

an

Interval

Timer interrupt. The

.LEVELO s UFPort for the I nterval

timet: allol's tlw

LrlV~Ll uset: to

keep track of cunning and

CPU

time, and to

set

time intervals.

5.3.1

CPU iND RUNNING TIME

The user

may

query the t:unning and

CPU

time

by

use of th

e QTIMER

instruction:

Query TIMEil QTIMED HX

The

first and

only opeeand address is

the address

of an

eight

byte scannout area,

aligned

on a

halfwot:d boundary.

After completion of the

QTIMER

insteuction, the

scannout

area contains

the

running

time

and CPU time

sillce

tne

last

I PL in timer uni ts

(100

usec.

) :

. r---, o

^{J Rea I}

^{T i rue}

^I

l 1

4 I l _ __ _ _ _ _ _ _ _ __

CP

U

ti me

J I

5.3.2 TINE

INTERVALS

0"'· _:.---- \

The

LEVELl us

h

r may set

a

time interval by placing

the

t:eal time at whicn

he

wishes to be

interrupted in

the Tiroer Unit

Control

Block

extension. When

that time is reached, LEVELO

will

signal

an interrupt to LEVEL

l.

One

instruction

is

provided

by

LEVELO for communications

with

the

META 4B.

The

META

4A can interrupt the

META

4B

and pass

i t

a code

using the INTB instruction:

INTerrupt meta 48

INTB

HX

-19-

The first and onl y operand address is passed to the META 48 to identify the interrupt.

This section Write, Read, EBCDIC.

describes the CPCs which aLe unit-dependent, i. e., and Special. Note that all data transfer is i n

01- Hrite. This command is invalid for the 3461 and, if encountered, causes the channel program to be aborted and

an Invalid CPC Program interrupt to occur. This is the case for all invalid CPCs for every unit.

02- Read. This co.mand causes by the length field to be the address in the CPC.

range 1 to 80, unpredictable 06- Special. Invalid.

01- Write. Invalid.

02- Read. I nvalid.

the number of bytes -,pecified read into memory starting at If the length is not in the results will occur.

16- Start Timer: The Timer begins to decrement location X'50' e very 100 microseconas.

06- Stop Timer.

01 or 11- Hrite or Write without Edit. The character string specified by the aadress and length fields is typed on the Typewriter, with trailing blanks removed and a carriage return appended. If an exact typing of the

-21-

string is desired, with trailing blanks and ¹¹⁰ carriage return, then bit 3 of the command should be set.

02 or 12- Read or Read without Edit. Input is accepted feom the keyboard until either a carriage return is typed or the length i s exhausted. If a Read is performed, as opposed to a Read without Edit, then two extra facilities are provided: Logical Backspace and Logical Line Delete.

If a logical backspace character is typed (LEVELl specifies this character in location 66), the previous character is ignored and removed from the input buffer.

If a logical line delete is typed (al so specified by LEVELl in location 67), the complete pr€ceeding input is ignored and the Read is restarted.

06- Special. Invalid •

.xl- Write. Data is written onto the pointed to by the CPC address.

follow in 9 format:

r---r---,

disk from the buffer This buffer has the

o

^{I reserved I}

\---+

- - - I 2 I sector address 1

i---+---1

4 I DATA I

\---+---1

I • I

• •

The length is rounded up to a halfword and used to determine the amount of data to write.

Any

amount may be writte n with one CPC. The sector address specifies the first sector on which data i s to be written; an automatic seek to this sector is performed by LBVELO. If the length is not a multiple of 640 bytes, the last sec tor Hill be filled with zeroes.

02 or 12- Bead or Read Check. The Read command uses the same buffer format as a Write , and pe rforms equivalently in terms of length specification, automatic seek, etc. The only differe nce is that data is read into the buffer dnd the length does specify the exact amount of data to t.rao.s fer.

Read Check is used to check data just written Oll the disk alld should be chained onto e ve ry Wri te for best performance.

The address and length fields should be identical to those in the Write.

06- Special. This CPC is used to callse a "stand-alone" seek of the carriage arm. T his can cause a pertorma nce increase ill certain s.ituatiolls where computing is to be done before a Read or Write - t he seek can operate concurrently with the computing. The address field points to a halfword containing the sector address to

~hich t he seek is do ne: t he le ngth field is ignored.

x1- Write. Either one or two on the specified are written

setting of bits 2 aod 3:

ba lfwords at the address lights, depending on the

00: 01 : 10:

11 :

No operation. Oll hal.t'word is o ae half·word is First halfwor:d t he next one

written on the lowers. written on the uppers.

is written on th~ uppers and

on the lowers. The length field i s ignored.

x2- the

Read. The half word at

contents of the data switches are r:ead into t he specified addres£; the length field is ignored.

x6- Special. I nva lid.

0 1- PIO Write. The halfword at perform a PIO write to t he fiel d is ignored.

the data address i s used to Vector GenEral. T he length

02- Read. The le ngth field divided by two specifies the number of consecutive register:s to be read from the Vector General into the memory location specifiell. '£he starting register address is determined by the last PIO Write CPC.

-23-

06 or 16- Allow Interrupts or Set Display Buffer Address.

The Allow Interrupts command is used to inform tI,e META 48 that it can again request interrupts. This CPC should be i ssued at the end of the interrupt handler for t I,e B.

In a Set Display Buffer Address command, the display buffer address specified in the CPC is sent to the Null META 4B so that i t can initialize for displaying.

Both of these CPCs ignore the length field.

This section lists and describes the events by LEVELO. In addition, the status data handling routine ill its automatic stocage is

that are pre-defined passed to the event explained.

The first halfKord of the status, and therefore of an Avent's automatic stoI:aqe, is always the event name that was originally signalled (as opposed to the name actually found in the EVL search). This is also true for events caused by LEVEL1 via lOhe SIGNAL instruction. The remaining status is vaciable, although two halfl,/Ords are comlllon:

Last (PC Address: On an I/O event, last CPC that WdS interpreted.

an ecrOI: condition arises.

this 1S the addI:ess of the Some CPCs may be ignored if

USH: On a.n I/O event, causing the event.

this is the final USH fI:om the unit

2001- The time of day placed in the UCB extention by LEVEL1 has been reached. statns is the running time (J2 bits) and CPU time (32 bits) at the time of the inteI:r upt, in timer units.

1031- META 4B intfJrrupt. Status is the cede specifieo in an INTA instruction executed on the META 4B.

1031- Null display enabled

~lETA 4B inteLrllpt. Status is the USH and the bu ffer add ress. Further .i n terr upts will be after an Allow InteI:I:upts CPC is executed.

-25-

The second he x digit of the event name fo~ these events is the unit add~ess of the local I/O unit.

7.4.1 3461 CARD READEll

2411- Ch an nel P~ogram Complete. Status i s Last CPC

Add~ess and USB.

2421- I/O Empty.

E~~or, caused by Read or Eeed Check, or Hopper Status is the same as 2411.

7.4.2 4132 KEYBOARD/TYPEWRITER

2611 - Channel Prog~am Complete.

l\dd~ess, USH, a nd Remaining Length is only meaningful on gives t he differ ence bet.een the CPC and the actual number

st atus is Last CPC Length. The Remaining Read commands, where i t

the length specified in of characters typed in.

2631- I nterrupt. Switch. St.atus i s USI1.

7.4.3 14114 DISK STORAGE UNIT

2211 - Channel Prog~am Complete. Status is Last (PC Address'and USH.

2221- Seek Check, caused if the sector number on an a utomatic or stand-al one seek cannot ce veei f ied aftee

t en r etries. status same as 2211.

7.222- I/O Error, caused by Rea d or Read Check commands i f a data teansfe~ error peLsists aiter 10 ~etLies.

Status is same as 2211 and 2221.

7.4.4 CONTROL PANEL

2531- Interrupt Button. There is no status other than the e vent name.

The event name for an SVC instruction is always COxx, ~here xx is the SVC code. No status other than the name i tself is

pa ssed.

The evant xx is the na me i tse l.E

name for a Program Program int .rrupt is passed, except

Interrupt is always DOxx, where code. No sta tus a ther than the

in the following cases:

operation- An image of the Program Interrupt Scan-out Area is passed, comprising five halfwords of s tatus.

Invalid CPC- The Last CPC A ddress is Fassed. Thi s CPC contains the invalid command.

This event is really LEVELl-defined, in initially . starting up the multi-programming maintenance. See

but is intended for use LEVELl system and in the appropriate LEVELl manual for an explanation.

As described in event entry was the event tral' na me of FOOO.

Section fa und in

EVL is

3.1, this event is used if the EVL search. The first used, and should have a

-27-

no other entry in standard

The following table lists the vBeious lowee memory aeeas in LEVELO which are accessabl e by LEVEL1:

2E I/O unit interrupt masK

30 OCB Table - Interval Timer DCB address 32 META 4B UCB address

34 1444 Disk Stdrage Onit DCB address 16

38 3461 Card Beader OCB address 3A Control Panel UCB address

]C 4132 Keyboard/Typewriter UCB address

3 E: META 4A UCB address

40 SIMALE UCB addeess

42 vector General

uee

^address

44 46 48

" A 4C 4E

50

5/360 Device 050 5/360 Device 051 5/ 360 Device 052 S/360 Device 053

Inteeva 1 Timer

OCB UCB lICB UCB

60 Parallel Queue head

address address addeess address

62 Pointer to predecessor of executing routi ne 64 Feee Memory List head

66 Logical Backspace character 67 Logical: Line Del ete Character 70 Event List heads - 'rimer e vents 72 ~I ETA 4B events

74 al l othee l ocal I/O unit events 76 5/360 events

78 )

n )

7C )

7E

>

events forLEVEL1 use

80 ) 82 )

84 )

86 )

88 SVC events

8A Program Interrupt events

Be

Program Manipulation events BE Event trap

- 29-

'rhe fol lowing table lists the Progra m inte rrupt codes that can occ ur on I,EVllL 1 :

2 Ope ra tion

8 Arithmet k Overflow A Conversion Overflo~

C Division by Zero

E Alignment

10 Register Specification 12 Privilege

14 Stack Overflow 16 Stack Underflow 18 Execute

20 No Free Memory

22 Invalid FREE instruction 24 Invalid CPC'

26 Zero S/360 DCD Address

The f ollowing table l ists the operation codes f or the LEVELO extended i nst ruc tion s;

Ui.2I!l.!KnQH

^S:;.QQll

v ENT BE

./ EXCP FD

.-FRllE 43

v FREER 03

v'G llT 41

v GE1'N AX 02 / GETR 01 , INTB G.F

v POS'f Fll

v'QT HI ER 64

",RET

OB

v SIG NiH FC

VWHT 71l

/"'.

WRITE 67 _{, y} ^>

-31-

/

.'-"'

Certain maccos ace provided for the LEVELl assembly language pcogrammer. ~heHe macros reside in the BUGS macro Iibcacy

(M4ALIB) and ace described in the following pacagraphs .

This macro gellerates an Event entry which can be placed on an EVL. I t is coded as follows:

[label] EVENT link.name,flags,entry-point [,priority,stack-frame-size]

The priority and stack frame size need only he coded for parallel routines .

These two mac ros describing the

coding:

label AU'l'O which generates:

LINE

I,

* *

LINE label OSECT

(J S IN G labelP OS labelN DS labelR OS labei A OS

are used in each routine to generate a DS ECT stack frame section. The DSECT is begun by

AUTOMATIC STORAGE MAP

label,SFP A

A 15H DC

PREV10US POINTER N EX T P

a

IN T El1 REGISTER SAVE AUTOMATIC STORAGh

Pollowing the A{]Tll, DS's for: t he automatic variables can be coded. Once al l the automatic space is defined, the pr:ogr:ammer s hould code:

EN OJ\ UTO which will gener:ate: labelL

f,SYSECT

EQU CSEC1' LINE

*-labelA AUTO STORAGE LENGTH

to end tile DSECT. The s ymbol "labelL" s hould be used in the ENT instr:ucticn to specify the length of the automatic storage desirerl. Do not f ocget to include space foe status data.

'1:'his macr:o i s used in a subr:outine to return a code ill one of t he r:egisters of the invoking routine. It is coded:

[label) RETCODE invoker-r:eg[,code I The r:etur:n code specifi ed in the

(reg) regist.er: i s placed in the routine specified by"invoke r-I:eg".

the p race ss.

(reg) ]

macro or contained in the register of the invoking

Regis te r 2 i s bashed in

Thi s macr:o i s used to genecate a CPC for: use with the EXCP illstruction.

[label] CPC commaud ,flags[ ,addr:ess[ ,length)]

If the address and/or l ength is set to zero in the generated CPC.

-33-

not coded, these fields are

I

This macr-o locations in the mac r-o is

gene rates an lower Ille mory available for

equa te table of the LEVELO-defined accessable by U;VEL1. A l is ting of those who need it .

• •