Theory of

OUVETTI

PERSDNAL

COMPUTER

M24 M21

PREFACE

The Olivetti L1 M24/M21 Theory of Operation Manual contains the descrip- tion of the circuit boards present in the basic module of the M24 and M21 Personal Computers. It also contains the description of some of the optional boards that can be used with the M24/M21 Personal Computers.

This manual is intended for field engineers, system specialists and laboratory engineers who need to maintain and repair the boards present in the M24 and M21 Personal Computers.

DISTRIBUTION: Internal (Z) FIRST EDITION: November 1984 REFERENCES:

M24/M21 M24

- Hardware Architecture and Function - code 4100710 W M21

M24 M24

TRADEMARKS:

- Service Manual - Service Manual - Schematics

- Spare Parts Catalogue

IBM is a registered trade mark of International Business Machines Corp.

NEC is a registered trade mark of Nippon Electric Corp.

Microsoft and MS-DOS are registered trade marks of Microsoft Corp.

Ethernet is a registered trade mark of Digital Research and Rank Xerox Corp.

Z8000 is a registered trade mark of Zilog Corp.

- code 4100670 S - code 4101680 C - code 4100750 S - code 4100740 Z

Intel is a registered trade mark of Intel Corp.

INS is a registered trade mark of National Semi-conductor Corp.

CP/M-86 is a registered trade mark of Digital Research.

OMNINET Transporter is a registered trade mark of Corvus Systems Inc.

DTC is a registered trade mark of Data Technology Corp.

PUBLICATION ISSUED BY:

PAGE

1 . SYSTEM DESCRIPTION 1-1 INTRODUCTION

1-1 CHARACTERISTICS 1-4 CIRCUIT BOARDS

2. MOTHERBOARD 2-1 INTRODUCTION

2-2 MOTHERBOARD BLOCK DIAGRAM 2-6 CENTRAL PROCESSOR UNIT 2-12 NUMERIC DATA PROCESSOR 2-14 DMA CONTROL LOGIC

2-21 INTERRUPT CONTROL LOGIC 2-25 CLOCK GENERATOR

2-28 BUS ARBITER 2-31 BUS CONTROLLER

2-33 PROGRAMMABLE WAIT LOGIC 2-35 RANDOM ACCESS MEMORY

2-42 PROGRAMMABLE READ ONLY MEMORY 2-43 INPUT/OUTPUT CHIP SELECT LOGIC 2-47 I/O ADDRESS MAP

PAGE

2-52 REAL TIME CLOCK AND CALENDAR 2-53 SPEAKER INTERFACE

2-54 KEYBOARD INTERFACE

2-58 MINI-FLOPPY DISK INTERFACE 2-69 PARALLEL PRINTER INTERFACE 2-71 SERIAL COMMUNICATION INTERFACE

3. BUS CONVERTER BOARD 3-1 INTRODUCTION

3-2 16 BIT DATA TRANSFERS 3-3 8 BIT DATA TRANSFERS

3-7 I/O EXPANSION BUS CONNECTORS 4. MEMORY EXPANSION BOARD

4-1 INTRODUCTION

4-1 MEMORY CONTROL LOGIC 4-3 MEMORY ADDRESSING

5. DISPLAY CONTROLLER 5-1 CHARACTERISTICS

5-2 OPTIONS DISPLAY BOARD 5-2 PRINCIPLES OF OPERATION 5-5 FUNCTIONAL DESCRIPTION

6. KEYBOARDS

7-2 MECHANICAL CHARACTERISTICS 7-3 FUNCTIONAL DESCRIPTION

8. APB Z8000 BOARD (APB 2481) 8-1 OVERVIEW

8-1 GENERAL DESCRIPTION 8-3 FUNCTIONAL DESCRIPTION 8-5 BUS HANDSHAKING

8-7 BUS HANDSHAKING TIMING 8-9 18001 PROCESSOR

8-12 PROGRAMMABLE READ ONLY MEMORY 8-13 RANDOM ACCESS MEMORY

8-22 I/O DEVICES

8-29 8251A SERIAL INTERFACE

A. DISPLAY CONTROLLER PAL AND ROM DESCRIPTIONS A-1 PAL 10L8 DESCRIPTION

A-7 PROM 27S19A CONTENTS A-9 SCRAMBLER EPROM

PAGE

8. LOGIC DIAGRAMS 8-1 MOTHERBOARD

8-14 DISPLAY CONTROLLER BOARD 8-31 PIGGY BACK BOARD

8-32 KEYBOARD

8-33 POWER SUPPLY UNIT 8-34 BUS CONVERTER BOARD 8-37 MEMORY EXPANSION BOARD 8-41 APB Z8000 BOARD

8-49 MULTI-FUNCTION COMMUNICATION INTERFACE BOARD

CONTENTS

PAGE

1 . SYSTEM DESCRIPTION 1-1 INTRODUCTION

1-1 . CHARACTERISTICS 1-4 CIRCUIT BOARDS 1-4 MOTHERBOARD

1-7 INDIGENOUS DISPLAY CONTROLLER BOARD 1-9 POWER SUPPLY BOARDS

1-10 KEYBOARDS

1-12 BUS CONVERTER BOARD 1-14 MEMORY EXPANSION BOARD 1-15 APB Z8000 BOARD (M24 Only)

1-16 DISPLAY CONTROLLER OPTIONS BOARD

INTRODUCTION

This manual gives a detailed functional description of the circuit boards which reside in the Olivetti M24/M21 Personal Computers. It also gives the functional description of the keyboard and some optional boards that can be inserted into the system.

CHARACTERISTICS

Basically the M24/M21 Personal Computers are made up of the processing unit and the associated peripheral units (that is, disk drives, display unit, printers, keyboard~. The processing unit and the peripheral control circuits reside in the Basic Module.

The Basic Module always contains the following circuit boards:

Motherboard

Indigenous Display Controller Power Supply

The basic module can be expanded by the addition of the following circuit boards:

Bus Converter Board Memory Expansion Board

Display Controller Options Board APB

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The last three boards can only be added to the system if the Bus Con- verter Board is present. In fact, they are plugged into the dual row con- nectors expansion slots of the Bus Converter Board.

SYSTEM BOX

MOTHERBOARD

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RAM ^DISKETTE PARALLEL SERIAL INTERFACE INTERFACE INTER FACE

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OLIVETTI

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Z8000 SOFT BOARD OPTIONAL DISPLAY CONTROLLER BOARD

- - - " -

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IBM COMPATIBLE EXPANSION BOARDS HDU CONTROLLER BOARD

IEEE 488 INTERFACE BOARD

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With the Bus Converter Board present, other IBM compatible boards can be added to expand the system. These include:

Hard Disk Controller

Ethernet Transporter Board Ominet Transporter Board IEEE 488 Interface Board

Twin RS232 Serial Interface Board Bisynchronous Communications Board Bit Oriented Communications Board Line Controller Unit Boards

These boards plug into the 62 pin connectors present on the Bus Converter Board.

CIRCUIT BOARDS

MOTHERBOARD

The motherboard is the main processing board of the M24/M21 systems. It is based on the 16 bit 8 MHz 8086 microprocessor and includes:

Central Processing Unit (CPU): A 16 bit 8 MHz 8086 microprocessor which controls all the arithmetic and logic circuits within the sys- tem. It has a direct addressing cap,ability up to 1 MB of memory, a 14 word by 16 bit register set and 24 operand addressing modes.

Numeric Data Processor (NDP) Socket: This socket is available so that

an 8087 Numeric Data processor can be installed as an option. This processor serves as a coprocessor attached to the 8086 CPU and effec- tively adds aO-bit floating point registers to the 8086 register set.

16KB of Read Only Memory (ROM): Two 8K ROM chips which contain the Power up Diagnostics, the Power on Bootstrap, the drivers for mini- floppy disk drives, hard disk units and peripherals, and the initial- ization programs for Large Scale Integration chips.

Random Access Memory (RAM): 128KB of RAM are available on the mother- board. These can be expanded up to 256KB with the insertion of 64K by 1 bit chips. When 256K by 1 bit chips are used the RAM can be expanded up to 512KB.

Memory Control Circuitry and Parity Checking: This circuitry provides all the timing signals for the transfer of data to and from memory.

It also multiplexes the addresses coming from the CPU and prepares them to address the particular memory location. The parity generation and checking circuitry generates a parity bit during a write opera- tion and is then read back and checked for any parity error.

Interrupt Handling Circuitry: It consists of an 8259 Interrupt Con- troller which is a programmable device that handles the priority interrupts to the CPU. It controls all the interrupts used In the system.

Bus Arbiter logic: The main component in this circuitry is the PAL 16R8 which handles the arbitration between the three bus masters namely the CPU, the DMA and an external processor.

DMA Circuitry: This is based on the 8237 DMA controller and it allows the external 1/0 devices to transfer information to/from RAM memory

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UPI - 8041 A UNIVERSAL PERIPHERAL INTERFACE

MICROCOMPUTER, KEYBOARD CONTROLLER J4 - PARALLEL PRINTER INTERFACE J5 - Z8350 CHANNEL B INTERFACE

Clock Calendar Chip with Battery Back Up:. This chip is used to pro- vide real time for the system. The battery back up is used to keep the device running even during a system power fail.

P.rallel Interface~~This interface provides the system with one Cen- tronics parallel port for connecting a printer.

Serial Interface: The motherboard uses an 8250 asynchronous communi- cation controller to provide an RS-232-C channel. It is possible to remove this chip and replace it with an 8530 Serial Communications Controller. The 8530 SCC is a USART (Universal Synchronous Asysnchro- nous Receiver Transmitter) and provides two serial channels.

Keyboard Interface: This interface is based on an 8041 microprocessor which is used to convert the system parallel data to serial data for the keyboard and vice-versa.

Fl~ppy Disk Interface:. The floppy disk interface is based on the uPD765 controller and it provides the circuitry required to drive and control two 5.25 inch mini-floppy disk drives.

INDIGENOUS DISPLAY CONTROLLER BOARD

The Indigenous Display Controller circuit board is a microprocessor based interface board for controlling colour and monochrome display units. It is based on a 6845 CRT controller and contains 32KB of RAM. It has a 4K or an 8 K byte ROM. With a 4KB ROM only the IBM character set is provided while with an 8KB ROM a second character set can be implemented.

The Display Controller can support the following modes of operation:

40x25 Alphanumeric Mode 80x25 Alphanumeric Mode

640x400 Monochrome Graphics Mode

640x200 IBM compatible Monochrome Graphics Mode

320x200 IBM compatible Colour Graphics Mode (with 12" Display Unit) 512x256, M20 compatible, Monochrome Graphics Mode (with APB Z8000 Board and 12" Display Unit present)

When in a colour mode, this controller can display four colours simul- taneously, chosen from a palette of 16. With a monochrome monitor, instead of the various colours, shades of grey are displayed.

This Display Controller contains the circuitry for providing the follow- ing character attributes:

Reverse Video Blinking Highlight Hide Underline

Other characteristics of this display controller include Degaussing and paging.

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POWER SUPPLY BOARDS

The Power Supply Unit provides the correct d.c. voltages for all the cir- cuit boards resident in the Basic Module, the keyboard, the disk drives and the monochrome display unit.

The circuitry lies on two boards enclosed in a metal case. It IS a switching type power supply with a line input of 110Vac or 220Vac select- able by an on board jumper. The voltage outputs are full wave rectified and· include the +5Vdc, +12Vdc, +15Vdc, -12Vdc voltages. The power supply circuitry also include overload/overvoltage protection for all voltages.

KEYBOARDS

Three different kinds of keyboards are used on the M24 and the M21 sys- tems:

Keyboard 1 - IBM compatible keyboard for M24 system Keyboard 2 - Native extended keyboard for M24 system M21 Keyboard - IBM compatible keyboard for M21 system

The three keyboards have the same circuitry but differ in their layouts and in the number of function keys.

The keyboard circuitry is based on the 8039 microprocessor with a 16K byte EPROM. This EPROM contains the keyboard tine, the scan "codes for all keyboard keys and a routine stuck keys. A 9 pin connector is also available to permit of a "mouse" to the keyboard.

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BUS CONVERTER BOARD

The Bus Converter Board is an optional board which when present provides 16 bit and 8 bit 1/0 expansion slots to the system. Thus it allows the simultaneous use of 16 bit Olivetti boards and 8 bit IBM compatible con- trollers.

It consists of an EPROM, addressed by a counter, which provides timing signals to enable and/or disable the required data buffers for 1/0 read or write operations to a controller.

This board contains two kinds of 1/0 bus connectors:

38 pin connectors to handle signals used by the 16 bit Olivetti boards.

62 pin connectors to handle signals used by both the 16 bit Olivetti boards and the 8 bit IBM compatible boards.

The M24 Bus Converter Board contains four 38 pin connectors and seven 62 pin connectors. The M21 Bus Converter Board contains one 38 pin connec- tor and three 62 pin connectors.

Fig. 1-8 M21 B us Converter Board

'MEMORY EXPANSION BOARD.

The Memory Expansion Board allows the expansion of the system RAM memory by a maximum of 384KB. It consists of 3 banks, each of 128KB, and each bank contains 2 groups of nine 64Kx1 RAM chips.

Besides the three RAM banks, this board also performs the memory control logic, address multiplexing, bus buffering and parity generation and checking required for the added RAM memory.

It is inserted in a slot on the Bus Converter Board and it is seen by the system as a 16 bit board and thus it can perform byte and word opera- tions.

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APB Z8000 BOARD (M24 Oniy)

The APB Z8000 board is a 16 bit board which is inserted in the M24 Bus Converter Board. The function of this board is to allow the M24 system to operate in a PCOS (M20 operating system) environment instead of the M24 operating system. This permits M20 programs to be run on the M24 personal computer.

It is based on the Z8001 4MHz microprocessor and contains 8K bytes of resident ROMs used for bootstrap and diagnostic routines. It provides its own RS232 serial communication channel and uses the random access memory, the DMA circuitry and the peripheral controllers present on the mother- board.

The APB Z8000 board contains the bus handshaking circuitry which permits the system bus to be assigned either to the Z8001 processor or to the 8086 processor resident on the motherboard.

Also present on the APB Z8000 board is an address translation PROM which changes the Z8001 addresses to the physical memory addresses.

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DISPLAY CONTROLLER OPTIONS BOARD

The Display Controller Options Board is an optional board which is inserted into the dual expansion slots on the Bus Converter Board. Its use is to upgrade the Indigenous Display Controller Board to a high per- formance display controller. It is connected to the indigenous display controller via a small flat cable while the Bus Converter Board acts as an interface between the options board and the M24 system.

This board provides additional display features to the M24 Indigenous Display Controller which include:

up to three additional 640 x 400 bit planes software controlled Look Up Table

ability to display 16 colours simultaneously

ability to display characters and graphics simultaneously blinking pixels in graphics modes

4 colour, 8 colour PCOS compatibility (with Z8000 softcard present) The presence of this board in this system permits the connection of more than one monitor. In fact the enhancement board outputs go on to a 25 pin D-type connector on the board itself. When only one monitor is present, it must be connected to the connector on this board. The monitor can be either colour or monochrome. A second monitor can be connected to the iQdigenous board.

CONTENTS

PAGE

2. MOTHERBOARD 2-1 INTRODUCTION

2-2 MOTHERBOARD BLOCK DIAGRAM 2-6 CENTRAL PROCESSOR UNIT 2-6 CPU PIN FUNCTIONS 2-8 GENERAL OPERATION 2-10 CPU - MEMORY OPERATION 2-11 CPU BUS OPERATION 2-11 CPU I/O OPERATION 2-12 NUMERIC DATA PROCESSOR

2-15 DMA CONTROLLER FUNCTIONAL DESCRIPTION 2-16 DMA OPERATION

2-16 DMA CIRCUITRY

2-19 DMA - DEVICE SERVICE 2-21 INTERRUPT CONTROL LOGIC 2-21 NON-MASKABLE INTERRUPT

2-22 MASKABLE PRIORITY INTERRUPTS 2-25 CLOCK GENERATOR

2-35 RANDOM ACCESS MEMORY 2-35 MEMORY CONTROL LOGIC 2-37 MEMORY ADDRESSING 2-40 MEMORY REFRESH

2-41 PARITY GENERATOR AND CHECKER 2-42 PROGRAMMABLE READ ONLY MEMORY 2-43 INPUT/OUTPUT CHIP SELECT LOGIC 2-44 INPUT/OUTPUT PORT SELECT LOGIC 2-45 SYSTEM CONFIGURATION PORT 66 2-46 SYSTEM CONFIGURATION PORT 67 2-47 I/O ADDRESS MAP

2-48 SYSTEM MEMORY ADDRESS MAP 2-49 TIMER

2-52 REAL TIME CLOCK AND CALENDAR 2-53 SPEAKER INTERFACE

2-54 KEYBOARD INTERFACE

2-54 COMMUNICATION BETWEEN 8041 AND KEYBOARD 2-56 TMS7000 BOARD

2-58 MINI-FLOPPY DISK INTERFACE 2-60 FLOPPY DISK CONTROLLER

2-63 WRITE PRECOMPENSATION CIRCUITRY 2-65 DIGITAL CONTROL PORT AND DECODER 2-66 CLOCK AND TIMING CIRCUITRY

PAGE

2-69 PARALLEL PRINTER INTERFACE 2-71 SERIAL COMMUNICATION INTERFACE

2-71 8250 ASYNCHRONOUS COMMUNICATIONS ELEMENT (ACE) 2-73 Z8530 SERIAL COMMUNICATION CONTROLLER

2-76 SERIAL INTERFACE SIGNALS AND CONNECTOR 2-78 MULTIFUNCTION COMMUNICATIONS INTERFACE

INTRODUCTION

The motherboard is the large printed circuit board that sits at the bot- tom of the system box with the component side facing down. It consists of four major functional blocks.

Processor/DMA Controller Memory (PROM and ROM) 1/0 peripheral interfaces 1/0 connectors

These functional blocks are connected by means of three system busses called A BUS, D BUS, and C BUS. Further busses are derived from these busses as explained later. Figure 2-1 shows the system Busses.

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READIWRITE MEMORY READ ONLY

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I/O PERIPHERAL INTERFACES

The A Bus carries the address information generated by the CPU, NDP or DMA Controller.

The following busses are derived from the A Bus:

The following busses are derived from the 0 bus:

MO Bus which carries data in and out of RAM memory and out of ROM memory

PO Bus which carries data in and out of the OMA segment register, I/O peripheral interfaces and the Interrupt Controller.

The C Bus carries all the control signals.

MOTHERBOARD BLOCK DIAGRAM

Figure 2-2 is a detailed block diagram of the motherboard.

list of the various modules and their function.

CENTRAL PROCESSOR UNIT (CPU)

Below is a

16 bit microprocessor chip that contains within itself the arithmetic and logic circuits which extract program instructions from memory, one at a time and execute them. The microprocessor used is the Intel 8086 which runs at a frequency of 8 MHz.

NUMERIC DATA PROCESSOR (NDP)

16 bit numeric data processor that provides the instructions and data types needed for high performance. It is available as an option.

CLOCK GENERATOR

The clock generator is a single chip clock generator/driver which sup- plies the system clock for the CPU (8MHz) and a 4MHz clock for the peri- pherals. The clock generator chip used is the Intel 8284A.

CLOCK BUFFER

Circuitry which receives the system and peripheral clocks from the clock generator, buffers them and repowers them. Clocks generated include:

ClK86 used mainly by CPU, NOP and Bus Controller; BClK8 used by other logic on the motherboard; XClK8 used by the I/O expansion boards. The integrated circuit used is a 74LS241.

BUS CONTROLLER

The Bus Controller utilizes the status outputs from the CPU to generate and buffer control signals. The chip used is the Intel 8288.

DMA CONTROL BUFFER

The lS245 bidirectional buffer serves two purposes. The first is to repower commands from the bus controller so that there is enough driving power for these signals to the I/O connector. The second is to repower

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I/O PORT SELECT LOGIC

l

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1/0 PORTS ~

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I/O INTERFACE

CPU ADDRESS LATCHES

Th~ CPU address is latched into the CPU Address Latches by the signal ALE (Address Latch Enable) from the Bus Controller. The Latch used is the 74LS373.

CPU DATA BUFFER

The CPU Data Buffer repowers the CPU data to the system D Bus. The buffer used is the bidirectional LS245.

BUS.ARBITER CIRCUITRY

This circuitry arbitrates among the three system bus masters to access the system bus. The three system bus masters are: 8086 CPU, 8237 DMA Controller and an external processor (the l8001 soft card for example).

The main component of this circuitry is the Programmable Array Logic (PAL) 16R8 which handles this bus arbitration.

WAIT LOGIC

Each processor bus cycle consists of at least 4 clock cycles. These are referred to as T1, T2, T3 and T4. In the event of a 'NOT READY' indica- tion being given by the addressed device, WAIT states (Tw) are inserted between T3 and T4. These WAIT states are generated by the programmable wait logic which mainly consists of a PROM and a counter. These circuits insert the exact number of WAIT states needed for all devices, except for DMA ones (for DMA devices one WAIT state is automatically inserted).

DMA CONTROLLER

Direct Memory Access Controller is the device which allows external 1/0 devices to transfer information directly to/from RAM memory. The integrated circuit used is the Intel 8237.

DMA SEGMENT REGISTER

A 4 x 4 74LS670 register file which provides four upper address bits (A16-A19) so as to permit the DMA Controller to address up to 1MB of memory.

DMA ADDRESS LATCHES

Latches used to interface the DMAC to the system A bus. Latches used are the 74LS373 and 74LS245.

RAM TIMING CIRCUITS

Circuitry which provides all the timing signals necessary to address memory and control the transfer of data or instructions to and from memory.

RAM ADDRESS MULTIPLEXER

Circuitry made up of multiplexers used to address RAM. The system memory can be addressed in bytes as well as in words addressing two bytes. The multiplexer used is the 745158. This 2:1 multiplexer is used to switch

RANDOM ACCESS MEMORY

Volatile memory which stores the Operating System, Interpreter, and all other user data and programs. Information stored in RAM may be altered.

This Personal Computer uses 64K by 1 bit dynamic RAMs or 256K by 1 bit dynamic RAMs.

RAM PARITY GENERATOR AND CHECKER

Circuitry which generates the parity bit that gets written into memory during memory write operations. Parity is read back and checked against data to see if there is any parity error. If any parity error IS

detected, the parity error flip-flop'is set and a CPU Non-Maskable Inter- rupt is generated. NMI is reserved for some event, as in this case, that cannot wait.

ERASABLE PROGRAMMABLE READ ONLY MEMORY (EPROM)

EPROM is used to store the power up diagnostics and bootstrap. It IS a non-volatile type of memory and its capacity IS 16KB

INPUT/OUTPUT CHIP SELECT LOGIC

Circuitry used as motherboard I/O address decoder. A PAL12L10 IS used as this decoder.

MINI-FLOPPY DISK CONTROLLER

The circuitry which provides all the logic and control necessary to con- trol and record data onto, or read from the 5.25 inch mini-floppy disks.

It also initially formats new disks. The LSI component used is the uPD765.

TIMER

Programmable device used to provide a real time clock, to time and request refresh cycles for DMA channel and to provide the tone generator for the audio speaker.

INTERRUPT CONTROL LOGIC

Programmable device that handles the priority interrupts to the CPU. It functions as an overall manager in the interrupt-driven system environ- ment. The LSI component used is the Intel 8259.

CLOCK CALENDAR CHIP

A battery backed-up clock calendar chip which provides real time such as seconds, minutes, hours, day of week, days and months for the system.

SERIAL COMMUNICATION CONTROLLER

The 8250 Asynchronous Communication Element is used to support serial communication and is configured to have an RS232-C channel. The 8250 ACE can be replaced by the Z8530 SCC to have an asynchronous/ synchronous communication channel.

PARALLEL PRINTER INTERFACE

CENTRAL PROCESSOR UNIT

The central processor unit is the heart of the motherboard. Its function is to extract program instructions from memory and execute them. It con- sists of an Intel 8086 microprocessor chip, which contains internally the arithmetic and logic circuits required for executing the program instruc- tions resident in memory.

The ?ystem can also use a Numeric Data Processor (NDP) which acts as a co-processor to the CPU. It provides other mathematical instructions for all data types needed for high performance computing. The NDP is an Intel 8087 chip and is an optional feature.

Externally, there are additional logic address decoding, timing and buffer elements which are necessary to address memory and to control data and instructions.

CPU PIN FUNCTIONS

Figure 2-3 shows the pin functions for the Intel 8086 microprocessor In maximum mode and a brief description of each pin follows:

GND vcc

AD14 AD15

AD13 A16/53

AD12 A17/S4

AD11 A18/S5

AD10 A19/S6

AD9 -BHE/S7

AD8 MN/-MX

AD7 -RD

AD6 -ROI-GTO (HOLD)

AD5 -RO/-GT1 (HlDA)

AD4 -lOCK (-WR)

AD3 -S2 (M/-IO)

AD2 -S1 (DT/-R)

AD1 -so (-DEN)

OSO (ALE)

ADO-AD15 Address/Data Bus (Input/Output, active high)

These lines constitute the multiplexed memory/IO address and data bus. AO is used to enable data onto the least significant half of the data bus, 00-07, in memory or I/O operations.

A16/S3-A19/S6 Address/Status (Output, active high).

During T1 these are the four most significant address lines for memory operations. During memory and I/O operationsy status information is available on these lines during T2,T3,Tw and T4. During 1/0 operations these status lines are low.

MN/-MX Minimum/Maximum (Input)

This is the input used to select mInlmum or maximum mode for the 8086.

In this case, maximum mode is used to support the 8087 NOP.

-BHE/S7 Bus High Enable/Status (Output, active low)

During T1 the -BHE signal is used to enable data onto the most signifi- cant half of the data bus 08-015. The 57 status information is available during T2,T3, and T4.

-52 to -SO Status Lines (Output, active low)

These are the status lines for memory/IO transactions, interrupt ack- nowledge, processor halt or passive state.

-52 -51 -SO

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

QSO-QS1 Queue Status (Output)

These lines are the status lines for queue.

-TEST Test (Input)

Function

Interrupt Acknowledge Read 1/0 port

Write I/O Port Halt

Code Address Read Memory Write Memory Passive

the 8086 internal instruction

This input is examined by the "wait" instruction. If it is low, execution continues, otherwise the processor waits in an "idle" state.

READY Ready (Input, active high)

This pin is used by addressed memory or I/O device to insert the required number of wait cycles. The READY signal from memory/IO is synchronized by the 8284A Clock Generator to form READY.

NMI Non-Maskable Interrupt (Input)

This is an edge triggered input which causes a type 2 interrupt. A tran- sition from a low to a high initiates the interrupt at the end of the current instruction. The NMI interrupt has the highest priority over the other interrupts.

INTR Interrupt Request (Input, active high)

This line is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter. into an interrupt acknowledge operation.

-lOCK lock (Output, active low)

This is to inform other system bus masters that the system bus won't be released while this pin is active.

-RD READ (Output)

This read strobe indicates that the processor is performing a memory or 1/0 read cycle. This is not used in the this system.

RESET Reset (Input, active high)

This causes the processor to terminate its present activity immediately.

ClK Clock (Input)

This provides the basic timing for the processor and bus controller.

GENERAL OPERATION

The internal functions of the Intel 8086 microprocessor are divided into two major functional units

Execution/Control Unit (EU) Bus Interface Unit (BIU)

As shown in figure 2-4, these units can interact directly but for the most part perform their functions separately.

EXECUTION UNIT BUS INTERFACE UNIT

I

RELOCATION

I

REGISTER FilE

r--

REGISTER FilE DATA POINTER, AND

INDEX REGS (SWORDS)

16-BIT ALU

FLAGS

SEGMENT REGISTERS

AND INSTRUCTION

POINTER (5 WORDS)

BUS INTERFACE

UNIT

6-BYTE INSTRUCTION

QUEUE

-TEST----~---~~---__, INT~

NMI~

-RQ/-GTO,l CONTROL & TIMING

HOLD - - - - + I

HlDA.----; __ ~--~~--~----~--~~

i i i i

ClK RESET READY MN/MX GND VCC

Fig. 2-4 8086 Functional Block Diagram

-BHE/S7 A19(S6 A16/S3 AD15 : ADO

-INTA, -RD, -WR

DT/-R, -DEN, ALE

-lOCK QSO, QS1

-S2, -Sl, -SO

The execution unit (EU) performs the basic processing functions, as it contains the data registers and the arithmetic logic unit (ALU). It accepts prefetched instructions from the BIU and returns unrelocated operand addresses to it. It then receives memory operands via the BIU,

The Bus Interface Unit (BIU) first prefetches instructions before they are required by the EU. It buffers them in a queue that can contain up to six bytes of instruction stream, to wait for decoding and execution.

The EU therefore does not need to wait for completion of a bus cycle before taking in a new instruction. The BIU also provides the functions related to operand fetch and store, address relocation, and bus control processing.

CPU - MEMORY OPERATION

The 8086 processor employs a 20 bit address bus to access a byte or word in memory. The memory is logically organized as a linear array of 1 Mbyte addressed as 00000 to FFFFF (hex). Each location is an 8 bit byte.

Word (16 bit) operands consisting of consecutive bytes can fallon either even or odd address boundaries. The processor provides two signals, -BHE and AO, to select and enable an odd location, an even location or both.

For address and data operands, the least significant byte of the word will be stored in the lower valued address location and the most signifi- cant byte in the next highest address location.

The BIU automatically performs the proper number of memory accesses, one if the word operand is on an even byte boundary and two if it is on an odd byte boundary.

Physically the memory is organized as a high bank (015-08) and a low bank (07-00) which are addressed in parallel by the processor's address lines A19-A1. Byte data with even addresses is transferred on the 07 - 00 bus lines while odd addressed byte data (AO high) is transferred on the 015- 08 bus lines.

-BHE AO

0 0 whole word

0 1 upper byte from/to odd address 1 0 lower byte from/to even address

1 1 none

CPU BUS OPERATION

The 8086 microprocessor has a combined address and data bus called a time multiplexed bus. This bus is demultiplexed at the processor with a single set of address latches.

Each processor bus cycle consists of at least four elK cycles referred to as T1,T2,T3 and T4. The address is emitted from the processor during T1 and transfer occurs on the bus during T3 and T4.

T2 is used for changing the direction during read operations. In the event of a "NOT READY" indication being given by the addressed device,

"WAIT" states (Tw) are inserted between T3 and T4. Periods can occur between 8086 driven bus cycles referred to as "Idle" states. The proces- sor uses them for internal housekeeping. During T1 of any bus cycle the ALE (Addressing latch Enable) signal is emitted by the bus controller. At the trailing edge of this pulse, a valid address and certain status information for the cycle may be latched. Status bits -SO to -52 are used by the bus controller to identify the type of bus transaction.

CPU I/O OPERATION

The 8086 microprocessor provides 64K addressable input or output ports.

1/0 space is addressable as if it were a single memory segment, without the use of segment registers. The I/O address appears in the same format as the memory address on bus lines A15-AO.

NUMERIC DATA PROCESSOR

The 8087 Numeric Oata Processor serves as a coprocessor attached to the 8086 CPU. It effectively adds eight 80-bit floating point registers to the 8086 register set. It uses its own instruction queue to monitor the 8086 instruction stream, executing only those instructions intended for it and ignoring the instructions needed for the 8086 CPU. The 8087 requires the same type of timing, power and bus structure as the 8086 in maximum mode. The 8087 NOP instructions include a full set of arithmetic functions as well as powerful exponential, logarithmic and trigonometric functions.

The 8087 NOP cannot run by itself as it needs the 8086 CPU to run the data, address and control busses which feed it instructions and operands.

Figure 2-5 shows how the NOP is attached to the 8086 CPU. There are several lines running directly between the NOP and the CPU, namely:

- The test-busy signal

- A request/grant (RQ/-GTO) line - Queue status (QS1, QSO) signals

The test input pin of the 8086 is connected to the BUSY output pin of the NOP. This allows the 8086 CPU to use the WAIT instruction before each NOP instruction and for the programmer to put an FWAIT instruction in the program following each NOP instruction which deposits data in memory for immediate use by the CPU. Then the numeric instruction gets translated to the indicated NOP numeric operation (with the preceding WAIT) and the FWAIT instruction is translated as the CPU WAIT instruction. While the 8087 NOP is executing a numeric operation, it puts a 1 on its busy pin (hence the test pin of the CPU is forced to a 1). While the 8086 CPU executes a WAIT instruction, it halts its activity until the test pin

(pin 23) is returned to its normal state(O).

Thus the sequence of an NOP numeric instruction followed by a CPU WAIT will cause the CPU to call the NDP and then wait until the NDP has fin- ished before proceeding.

The request/grant line RQ/-GTO is used by the NOP to gain control of the bus which is shared by the NOP and CPU. This request/grant on the NOP line is connected to the RQ/-GT1 of the 8086 CPU. This is a two way com- munication line. A signal (request) from the NOP to the CPU indicates that the NOP wants to use the bus. Before the NOP can take the bus it must wait for the return signal (grant) from the CPU. When the NOP fin- ishes with the bus it sends a signal back to the CPU on the same line to indicate this. Thus, it is the NOP which requests the bus, and the CPU is the device which grants the bus as soon as it can after such a

There are two queue pins, QS1 and QSO, which help the NDP to keep its instruction queue synchronized with the CPU's. The two bits are used to encode the four possible states:

QS1 QSO

°

⁰

o

¹

1 0

1 1

CLOCK GENERATOR

Function No operation

First Byte of instruction Empty the queue

Subsequent byte of an instruction

CPU

_ - - - t •• ClK

ClK J.-.---.~--i ... ClK

Fig. 2-5 8087 NDP - 8086 CPU Connection

BUS INTERFACE

DMA CONTROL LOGIC

w;,.,-'-

DMA stands for Direct Memory Access and the main component of the DMA circuitry is the Intel 8237 DMA Controller. The DMA Controller is the device which takes over the system bus to transfer information directly from the 1/0 devices to the system memory and vice versa. This is neces- sary because blocks of data often have to be moved very rapidly.

The DMA circuitry is mainly made up of:

DMA Controller

DMA Segment Register DMA Control Buffer

D~.A Data Buffer DMA Address Latches

A simple DMA transfer usually takes place as follows: The DMA Controller is told to make a transfer either by the CPU or other device; then the DMA Controller makes a request to gain control of the bus from the CPU, other processors, or controllers which might currently be using the bus;

these other devices then relinquish control of the bus by putting their lines into the tri-state condition (electrically disconnecting the lines); they then grant the bus to the DMA Controller. Finally, the DMA Controller takes over the bus, generating its own address and control signals for the bus and causing the transfer of information.

CONTROL

CPU COMPLEX

DATA

DMA CONTROLLER

ADDRESS

DEVICE A DEVICE 8

DMA CONTROLLER FUNCTIONAL DESCRIPTION

The DMA Controller used on the system is the Intel 8237. Figure 2-7 is a block diagram of the DMA Controller (DMAC).

AEN ADSTB -MEMR -MEMW

HLDA HRQ DACKO:

DACK3

TIMING AND

DECREMENTOR TEMP WORD COUNT REG (16)

READ BUFFER BASE

16 BIT BUS 16 BIT BUS

INC/DECREMENTOR TEMP ADDRESS

REG (16)

READ/WRITE BUFFER

Fig. 2-7 DMA Controller (8237) Block Diagram

COMMAND CONTROL

A4: A7

>

The DMA Controller (DMAC) contains three basic blocks of control logic.

The Timing Control Block that generates internal timing and external con- trol signals for the DMAC.

The Program Command Control Block that decodes the various commands given to the DMAC by the microprocessor prior to servicing a DMA request. It also decodes the Mode Control word used to select the type of DMA during the servicing.

The Priority Encoder Block that resolves priority contention between DMA channels requesting service simultaneously. Channel 0 has the highest

Channel 1 is connected to the I/O expansion bus to support high speed data transfer between I/O devices and memory.

Channel 2 is dedicated to the mini-floppy disk controller for transfer- ring information to/from the minifloppy disk drive.

Channel 3 is connected to the I/O expansion bus to support high speed data transfer between I/O devices and memory.

DMA OPERATION

The DMA is designed to operate in two major cycles, the idle cycle and the active cycle.

Each device cycle is made up of a number of states. The DMAC can assume seven separate states, each composed of one full clock period. State I (51) is the inactive state. It is entered when the DMAC has no valid DMA requests pending. While in 51 the DMAC is inactive but may be in the Program Condition, being programmed by the processor.

State 0 (SO) is the first state of the DMA service, when the DMAC has requested a hold but the processor has not yet returned an acknowledge.

The DMAC may still be programmed until it receives HlDA (hold ack- nowledge) from the CPU. An acknowledge from the CPU indicates that DMA transfers may begin.

51, 52, 53 and 54 are the working states of the DMA service. If more time is needed to complete a transfer than is available with normal tim- ing, one WAIT cycle must be inserted. This is automatically inserted by part of the programmable WAIT logic

The WAIT state is inserted between 52 READY line (DMARDY) on the DMAC.

directly from the 1/0 device to memory -MEMW (or -MEMR and -lOW) being active read into or driven out of th~ DMAC in transfers.

DMA CIRCUITRY

or 53 and 54 by the use of the Note that the data is transferred (or vice versa) with -lOR and at the same time. The data is not 1/0 to memory or memory to 1/0 DMA

The DMAC issues a DMA Hold Request Acknowledge DMAHRQA whenever there is at least one valid DMA request. DMAHRQA goes to an l5244 latch pin 8 and is output as DMAHRQ. DMAHRQ then inputs a 745174 D latch which is clocked by the signal -elKS. The output 5DMAHRQ is one of the inputs to

Figure 2-8 shows the DMA circuitry used on the system.

AO-A19

~ ,~ J~TO I/O CONNECTOR

DMA CTRL BUFFER ~AHLDA ADDRESS LATCH

~

...

I '<t

« a:l

~

AO- A3 A4-A7

PDO - 3

:>

DMA SEGMENT

,...

... BAO

... BAl

~ ...

~ H LOA

H RQA

I-w

~ ifl

() a:

MWR

3! c::

:2; :2;

UJ w

:2; :2;

I I

CONTROL BUS MRD

4 - - - ' lOR

lOW

DO - D7 DATA BUFFER

Fig. 2-8 DMA Circuitry

DMAC

c:: 3!

Q Q

I I

DBO - 7

C"l C"l

I I

0 0

a ~

w ()

a: «

0 0

PDO - 7

=>

ADDRESS LATCH

The PAL outputs -DMAHLDA (DMA hold acknowledge) and -P86GT become active.

The -DMAHLDA does a number of things:

It passes through an inverter (LS04) to become DMAHLDA and then goes

It is input to pin 1 of the DMA Control Buffer and its effect is to change the direction of data flow through the buffer from B to A.

This enables the DMAC to dialogue with devices such as expansion memory boards and 1/0 boards not on the motherboard.

It enables the DMA address latch and the BA bus buffer to permit the DMA Controller to transfer bytes from the BA and DMA busses onto the A bus.

The generation of the signal -P86GT from PAL16R8 has the effect of disa- bling the CPU Address Latches and the CPU Data Buffers and the command lines from the Bus Controller. Hence the Address, Data and Control Busses are isolated from the CPU.

The DMAC now assumes control of the system busses.

The address for the first transfer operation comes out in two bytes. The least significant 8 bits (BAO-BA7) are output onto the the address bus via the BA bus buffer while the most significant 8 bits (PDO-PD7) are first strobed into the DMA address latch by the signal ADSTB before being output onto the address bus to complete the full 16 bits of the address bus. After the initial transfer takes place , the latch is updated only after a carry or borrow is generated in the least significant address byte.

DMAC supports 16 bit addresses which allow addressability to 64KB of memory. In order to make it able to address 1MB of memory as the CPU does, a 4 x 4 register file is used to provide the upper 4 bits DA16- DA19. This register file is named DMA segment register and is programm- able by software to address any 64KB block within 1MB of memory space.

On the following page is a timing diagram showing the sequence of some of the signals used during a DMA operation.

ClK8

I I

I I~

SDMAHRQ

- I

I 'I 86GT

/

~,

DMAHlDA

\_---

P86WAIT

I I

DMACYl

-...l L

Fig. 2-9 Timing Diagram

DMA - DEVICE SERVICE Idle Cycle

When no channel is requesting service, the DMAC will enter the idle cycle and perform SI states. In this cycle the DREQ lines are sampled every clock cycle to determine if any channel is requesting a DMA service. When -CS is low and HLDA is low, the DMAC enters the program condition and address lines AD to A3 address the control register to be loaded or read.

The -lOR and -lOW lines are used to select and to time reads or writes.

Active Cycle

When the DMAC is in the Idle Cycle and a channel requests a DMA service, the DMAC will output an HRQ and enter the active cycle. It is in this cycle that the DMA service will take place, in one of four modes: