Pad Layout

SED1750

Contents

OVERVIEW ... 4-1 TERMINAL FUNCTIONS ... 4-7 ABSOLUTE MAXIMUM RATINGS ... 4-11

OVERVIEW

The SED1750 is an MLS (Multi Line Selection) driving, 160 output, triple-value low resistance common (low) driver which can realize high picture quality and high speed responses.

Receiving signals from an LCD controller such as the SED1335 or SED1351, it works to make 4-line MLS drives in combination with the SED1580 or in combination with the SED1590 receiving signals direct from the MPU. Employing the SCI7500 as the power IC, the power to use for the MLS drive liquid crystal display system can be prepared easily.

Adopting a slim chip shape which is more advantageous to realize narrower borders with the LCD panels, the SED1750 is capable of making low voltage logic power operations and is applicable to a wide range of applications.

Owing to its pad layout designed to facilitate its installation to the substrate and thanks to its two-way choices of the driver output sequence, the highest working efficiency can be acquired with a 1/160 or 1/

320 duty panel.

Features

• LCD driver outputs ... 160

• Low output ON resistance

• High duty drive supported ... 1/320 (Reference value)

• Broad range of LC drive voltages ... + 14 to + 42 V (VCC = 2.7 to 5.5 V)

• Output shift direction pin select is possible

• Can be switched between 140 and 160 outputs

• Non-biased display OFF function

• Logic system power source ... 2.7 V to 5.5 V

• LC power source offset bias can be adjusted relative to the VDDH and GND levels

• Slim chip shape

• D0B... Au Bump die

• T0A... TCP

Pad Layout

Y Die.No.

X 179

1 180

203

68

43 67

44

Chip size 15.62 mm × 2.47 mm Pad pitch 80 µm (Min.) Chip thickness 525 µm ± 25 µm

1) Au Bump Specifications (SED1750DOB) Reference Values Only Au vertical bump

Parallel to Scribe × Perpendicular to Scribe ± Tolerance

Bump Size A 60 µm × 75 µm ± 4 mm (Pad No. 1 to 43, 68 to 179) Bump Size B 80 µm × 50 µm ± 4 mm (Pad No. 44 to 67, 180 to 203)

Bump height 17 to 28 µm (The details specified in the acceptance specifications.)

Units: µm

Pad Coordinates

51 COM8 7655 -375

52 COM9 -295

53 COM10 -215

54 COM11 -135

55 COM12 -55

56 COM13 25

57 COM14 105

58 COM15 185

59 COM16 265

60 COM17 345

61 COM18 425

62 COM19 505

63 COM20 585

64 COM21 665

65 COM22 745

66 COM23 825

67 COM24 905

68 COM25 7419.3 1083 69 COM26 7285.6 70 COM27 7152 71 COM28 7018.3 72 COM29 6884.7 73 COM30 6751 74 COM31 6617.3 75 COM32 6483.7 76 COM33 6350 77 COM34 6216.3 78 COM35 6082.7 79 COM36 5949 80 COM37 5815.3 81 COM38 5681.7 82 COM39 5548 83 COM40 5414.3 84 COM41 5280.7 85 COM42 5147 86 COM43 5013.3 87 COM44 4879.7 88 COM45 4746 89 COM46 4612.3 90 COM47 4478.7 91 COM48 4345 92 COM49 4211.4 93 COM50 4077.7 94 COM51 3944 95 COM52 3810.4 96 COM53 3676.7 97 COM54 3543 98 COM55 3409.4 99 COM56 3275.7 100 COM57 3142

Pin Name X Y

101 COM58 3008.4 1083 102 COM59 2874.7 103 COM60 2741 104 COM61 2607.4 105 COM62 2473.7 106 COM63 2340 107 COM64 2206.4 108 COM65 2072.7 109 COM66 1939 110 COM67 1805.4 111 COM68 1671.7 112 COM69 1538.1 113 COM70 1404.4 114 COM71 1270.7 115 COM72 1137.1 116 COM73 1003.4 117 COM74 869.7 118 COM75 736.1 119 COM76 602.4 120 COM77 468.7 121 COM78 335.1 122 COM79 201.4 123 COM80 67.7 124 COM81 -67.7 125 COM82 -201.4 126 COM83 -335.1 127 COM84 -468.7 128 COM85 -602.4 129 COM86 -736.1 130 COM87 -869.7 131 COM88 -1003.4 132 COM89 -1137.1 133 COM90 -1270.7 134 COM91 -1404.4 135 COM92 -1538.1 136 COM93 -1671.7 137 COM94 -1805.4 138 COM95 -1939 139 COM96 -2072.7 140 COM97 -2206.4 141 COM98 -2340 142 COM99 -2473.7 143 COM100 -2607.4 144 COM101 -2741 145 COM102 -2874.7 146 COM103 -3008.4 147 COM104 -3142 148 COM105 -3275.7 149 COM106 -3409.4 150 COM107 -3543

Pin Name X Y

Pin Name X Y

1 VDDH -7522 -1045

2 +V1 -7427

3 VC -7332

4 -V1 -7237

5 VSS -7142

6 SHL -6804

7 SEL -6579

8 VCC -6241 9 LSEL -5902 10 DOFF -5538

11 FR -4791

12 DM -4323

13 DM -3943

14 DM -3563

15 DM -3183

16 DM -2803

17 CSEL -2336

18 LP -1998

19 DM -1162

20 CIO2 -755

21 DM -347

22 DM 0

23 DM 347

24 CIO1 755

25 DM 1162

26 YD 1998

27 DM 2336

28 DM 2803

29 DM 3183

30 DM 3563

31 DM 3943

32 DM 4323

33 DM 4791

34 DM 5538

35 F1 5902

36 DM 6241

37 F2 6579

38 TEST1 6804

39 VSS 7142

40 -V1 7237

41 VC 7332

42 +V1 7427

43 VDDH 7522 44 COM1 7655 -935

45 COM2 -855

46 COM3 -775

47 COM4 -695

48 COM5 -615

49 COM6 -535

50 COM7 -455

169 COM126 -6082.7 1083 170 COM127 -6216.3 171 COM128 -6350 172 COM129 -6483.7 173 COM130 -6617.3 174 COM131 -6751 175 COM132 -6884.7 176 COM133 -7018.3 177 COM134 -7152 178 COM135 -7285.6 179 COM136 -7419.3 180 COM137 -7655 905

181 COM138 825

182 COM139 745

183 COM140 665

184 COM141 585

185 COM142 505

186 COM143 425

Pin Name X Y

187 COM144 -7655 345

188 COM145 265

189 COM146 185

190 COM147 105

191 COM148 25

192 COM149 -55

193 COM150 -135

194 COM151 -215

195 COM152 -295

196 COM153 -375

197 COM154 -455

198 COM155 -535

199 COM156 -615

200 COM157 -695

201 COM158 -775

202 COM159 -855

203 COM160 -935

Pin Name X Y

Pin Name X Y

151 COM108 -3676.7 1083 152 COM109 -3810.4 153 COM110 -3944 154 COM111 -4077.7 155 COM112 -4211.4 156 COM113 -4345 157 COM114 -4478.7 158 COM115 -4612.3 159 COM116 -4746 160 COM117 -4879.7 161 COM118 -5013.3 162 COM119 -5147 163 COM120 -5280.7 164 COM121 -5414.3 165 COM122 -5548 166 COM123 -5681.7 167 COM124 -5815.3 168 COM125 -5949

TERMINAL FUNCTIONS

Input Terminator

TEST1

Terminal Name I/O Function Number of

Terminals COM1 to

O Common (row) output to drive LC.

COM160 Output transition occurs on falling edge of LP. 160 Carry signal I/O.

CIO1 I/O This is set to input or output depending on the level of CIO2 the SHL input. Output transition occurs on falling edge 2

of LP.

YD I Frame start/pulse input, with terminator. (*1) 1 F1, F2 I Drive pattern select signal input, with terminator. (*1) 2 LP I Shift clock input for display data.

(Triggers on falling edge.) With terminator. (*1) 1

Shift direction select and CIO terminal I/O control input.

SHL I 1

The numbers in parentheses are for 140 output mode.

Select input for the number of COM output terminals:

SEL I 160 outputs ←→ 140 outputs L: COM1 to COM160 1 H: COM9 to COM148

LSEL I 1/2 H operation select signal input.

L: Normal operation. H: 1/2 operation. 1

Chip select signal input for when a cascade connection

CSEL I is used.

L: Leading chip 1 H: Other chips

FR I LC drive output AC signal input. With terminator (*1) 1 LC display blanking control input. With a low level input, DOFF I all common outputs are temporarily set to the VC level.

The contents of the latches are maintained. With 1 terminator (*1)

TEST1 I Test1 signal input. Normally tied at L. 1

VCC, GNDL,

PowerPower source for logic:

GNDR GND: 0 V , VCC: +2.7 to 5.5 V 3 VCL, VCR,

LC Drive Power:

+V1L, +V1R,

Power GND: 0 V, 8

-V1L, -V1R,

VDDH: + 14.0 to 42.0 V, VDDH≥ +V1≥ VC≥ –V1≥ GND VDDHL, VDDHR

DM Dummy pad 19

Total 203 Note: *1

SHL Output Shift Direction

CIO1 CIO2

L 1(9) → 160(148) Input Output

H 160(148) → 1(9) Output Input

Block Diagram

VDDHL GNDL +V1L VCL –V1L DOFF

VDDHR GNDR +V1R VCR –V1R

CIO2 LCD Driver: 160-bits

Level Shifter: 3x160-bits

Decoder

Bi-directional Shift Register: 40-bits Data Register:

160-bits VCC

TEST1

LP YD CIO1

COM 1 COM 160

SHL SEL LSEL CSEL

FR F1 F2

Explanation of Each Block

Shift Register

This is a bi-directional shift register used for transmitting common data. The display data shifts on the falling edge of LP.

Level Shifter

The level shifter is a voltage level converter circuit which converts the signal voltage level from a logic system level to the LC driver system voltage level.

LCD Driver

The LCD driver outputs the LC drive voltage.

The relationship between the display blanking signal DOFF, the field recognition signals F1 & F2, the AC signal FR, and the common output voltage is as follows:

DOFF H L

FR L H —

F1,F2 1,1 0,1 1,0 0,0 1,1 0,1 1,0 0,0 —

Line 1 +V1 +V1 –V1 +V1 –V1 –V1 +V1 –V1 VC

Line 2 –V1 +V1 +V1 +V1 +V1 –V1 –V1 –V1 VC

Line 3 +V1 –V1 +V1 +V1 –V1 +V1 –V1 –V1 VC

Line 4 +V1 +V1 +V1 –V1 –V1 –V1 –V1 +V1 VC

Voltage level relationships: + V1 > VC > –V1 (VC is the center voltage level)

Timing Diagram (1) 1/320 duty, normal operation.

SHL = L, SEL = L, LSEL = L, CSEL = L (This diagram provided only as a reference.)

+V1 VC –V1

F2 F1 FR LP

Driver 1 COM1

+V1 VC –V1 COM2

+V1 VC –V1 COM3

+V1 VC –V1 COM4

+V1 VC –V1 COM5

+V1 VC –V1 COM6

+V1 VC –V1 COM7

+V1 VC –V1 COM8

+V1 VC –V1 Driver 2 COM160

Field 1 Field 2 Field 3

1 Frame (320 lines)

Field 4

1 2 3 80 8182 83 160 161 162 163 240 241 242 243 320 1 2 3

1

1 2 3 4 5 40 41 42 43 80 81 82 83 120 121 122 123 160 161 162 163

2 3 4 5

320 lines

160 161 162 163 320 1 2 3 4

YD LP FR

LP CIO 1 CIO 2

Timing Diagram (2) 1/320 duty, 1/2 H operation.

SHL = L, SEL = L, LSEL = H, CSEL = L (This diagram provided only as a reference.)

+V1 VC –V1

F2 F1 FR LP

Driver 1 COM1

+V1 VC –V1 COM2

+V1 VC –V1 COM3

+V1 VC –V1 COM4

+V1 VC –V1 COM5

+V1 VC –V1 COM6

+V1 VC –V1 COM7

+V1 VC –V1 COM8

+V1 VC –V1 Driver 2 COM160

Field 1 Field 2 Field 3

1 Frame (320 lines)

Field 4

2/320 2/1 2/80 2/81 2/160 2/161 2/240 2/241 2/320 2/1

1/1 1/2 1/81 1/82 1/161 1/162 1/241 1/242 1/1 1/2

1/1

1/1

2/1 1/2

2/2 1/3 1/40

2/40 1/41

2/41 1/80

2/80 1/81

2/81 1/120

2/120 1/121

2/121 1/160

2/160 1/161

2/161 2/1 1/2 2/2 1/3

320 lines

1/160 2/161 1/162 2/163 2/320 1/1 2/1 1/2 2/2 YD

LP FR

LP CIO CIO 1 2

ABSOLUTE MAXIMUM RATINGS

Item Signal Rated Value Units

Power voltage (1) VCC –0.3 to +7.0 V

Power voltage (2) VDDH –0.3 to + 45.0 V

Power voltage (3) ± V1, VC GND – 0.3 to VDDH + 0.3 V

Input voltage VI GND – 0.3 to VCC + 0.3 V

Output voltage VO GND – 0.3 to VCC + 0.3 V

CIO output current IO1 20 mA

Operating temperature Topr –30 to +85 °C

Storage temperature 1 Tstg1 –65 to +150 °C

Storage temperature 2 Tstg2 –55 to +100 °C

NOTE 1: The voltages are all relative to GND = 0 V.

NOTE 2: Storage temperature 1 is for the chip alone, and storage temperature 2 is for the TCP product.

NOTE 3: Ensure that the relationship between +V1, VC, and –V1 is always as follows:

VDDH ≥ +V¹ ≥ V^C ≥ –V¹ ≥ GND.

NOTE 4: The LSI may be permanently damaged if the logic system power is floating or VCC is less than or equal to 2.6 V when power is applied to the LC drive system. Special caution must be paid to the power sequences during power up and power down.

VCC

GND (–V1) VDDH/2 (VC) VDDH (+V1)

Logic System LCD System

Electrical Characteristics

DC Characteristics

Unless otherwise noted, GND = 0 V, VCC = + 5.0 V ± 10%, Ta = –30 to 85°C

Item Signal Parameter Applicable

Min Typ Max Unit

Terminals Power Supply

VCC VCC 2.7 5.0 5.5 V

Voltage (1) Range Operating

VDDH Function VDDH 8.0 42.0 V

Voltages Power Supply

+V1 Recommended Value +V1 VDDH V

Voltage (2) Power Supply

VC Recommended Value VC VDDH/2 V

Voltage (3) Power Supply

–V1 Recommended Value –V1 GND V

Voltage (4) High-level Input

VIH 0.8VCC V

Voltage

VCC = 2.7 to 5.5V Low-level Input

VIL 0.2VCC V

Voltage High-level Output

VOH IOH =

VCC–0.4 V

Voltage

VCC = 2.7 to 5.5V –0.3mA

CIO1,CIO2 Low-level Output

VOL IOL =

0.4 V

Voltage 0.3mA

Input Leakage Current ILI GND ≤ V^IN ≤ V^CC 2.0 µA

Input/Output Leakage

ILI/O GND ≤ VIN ≤ VCC CIO1,CIO2 5.0 µA

Current

Static Current IGND VDDH = 14.0~42.0V

GND 25 µA

VIH = VCC, VIL = GND

∆V^ON = 0.5 V VDDH = 0.55 0.7

Output Resistance RCOM Recommended +30.0V COM1 to kΩ

parameter VDDH = COM120

0.5 0.7 +40.0V

VCC = +5.0 V, VIH = VCC

VIL = GND, fLP = 22.4 kHz

12 25

Average Operating fFR = 70 Hz,

Consumption Current ICC Input data: 1/320 No load VCC µA

(1) VCC = 3.0 V

All other parameters 8 17

the same as VCC = 5.0 V.

VDDH = +V1 = +30.0 V, Average Operating VC = VDDH/2, –V1 = 0.0 V,

Consumption Current IDDH VCC = 5.0 V VDDH 7 13 µA

(2) All other parameters

the same as the ICC item.

Input Terminal

CI Freq. = 1 MHz 10 pF

Capacity

Chip alone Input/Output Terminal

CI/O Ta = 25°C CIO1,CIO2 18 pF

Capacity

CIO1,CIO2,FR, YD,LP,SHL,SEL,

LSEL,CSEL, DOFF,F1,F2, TEST1

LP,YD,SHL,SEL, LSEL,CSEL,F1, F2,DOFF,TEST1,

FR

LP,YD,SHL,SEL, LSEL,CSEL,F1,F2,

DOFF,TEST1,FR

Range of Operating Voltages: VCC – VDDH

It is necessary to set the voltage for VDDH within the VCC – VDDH operating voltage range shown in the diagram below.

Range of Operating Voltage 50

42 40

30

20

10 28

8

0

2.0 2.7 3.0 4.0

VCC (V) VDDH (V)

5.0 5.5 6.0

AC Characteristics

Input Timing Characteristics

The FR latched at the nth LP is reflected in the output at the n+1th LP.

tDS tDH

tSET tWCLH tWCLL

tCCL

tFFDS tFFDH tr tf

tFRDS tFRDH

FR

F1, F2

LP YD CIO1, 2 (IN)

(VCC = +5.0 V ± 10%, Ta = –30 to +85°C)

Item Signal Parameter Min Max Units

LP Frequency

t

CCL 500 ns

LP “H” Pulse Width

t

WCLH 55 ns

LP “L” Pulse Width

t

WCLL 330 ns

FR Setup Time

t

FRDS 100 ns

FR Hold Time

t

FRDH 40

F1, F2 Setup Time

t

FFDS 100

F1, F2 Hold Time

t

FFDH 40

Input Signal Rise Time

t

r 50 ns

Input Signal Fall Time

t

f 50 ns

CIO Setup Time

t

DS 100 ns

CIO Hold Time

t

DH 40 ns

YD → LP Allowable Time

t

SET 80 ns

(VCC = +2.7 V to 4.5 V, Ta = –30 to +85°C)

Item Signal Parameter Min Max Units

LP Frequency

t

CCL 800 ns

LP “H” Pulse Width

t

WCLH 100 ns

LP “L” Pulse Width

t

WCLL 660 ns

FR Setup Time

t

FRDS 200 ns

FR Hold Time

t

FRDH 40

F1, F2 Setup Time

t

FFDS 200

F1, F2 Hold Time

t

FFDH 40

Input Signal Rise Time

t

r 100 ns

Input Signal Fall Time

t

f 100 ns

CIO Setup Time

t

DS 200 ns

CIO Hold Time

t

DH 40 ns

YD → LP Allowable Time

t

SET 150 ns

Output Timing Characteristics

tpdCDOF

tpdCCL

tpdDOC LP

DOFF

COM Output CIO1, 2 (OUT)

(VCC = 5.0 V ± 10%, VDDH = +14.0 to +42.0 V, Ta = –30 to +85°C)

Item Signal Parameter Min Max Units

Delay time from LP to CIO output

t

pdDOC CL = 15 pF 300 ns Delay time from LP to COM output

t

pdCCL VDDH= 350 ns Delay time from DOFF to COM output

t

pdCDOF 14.0 V to 40.0 V 700 ns

(VCC = +2.7 V to 4.5 V, VDDH = +14.0 to +28.0 V, Ta = –30 to +85°C)

Item Signal Parameter Min Max Units

Delay time from LP to CIO output

t

pdDOC CL = 15 pF 600 ns Delay time from LP to COM output

t

pdCCL VDDH= 500 ns Delay time from DOFF to COM output

t

pdCDOF 14.0 V to 40.0 V 1400 ns

The Power Supply

Method of Forming Each Voltage Level

VCC GND

Logic System LCD Controller

Capacitor Coupling

Logic System LCD System SED1590 SED1580

Logic System LCD System SED1750 VDDx

VSSx

VDDy VSSy V3

VC VC

V1

–V1 V2

–V2 –V3

When the SED1590 (SED1580) and the SED1750 are used to form an extremely low power module system, the power relationships as shown in the figure above between the SED1590 (SED1580) and SED1750 logic systems, and the LCD system power supply, and the LCD controller power supply are optimal.

In this case, care is required when it comes to signal propagation in the logic system.

LCD Controller → SED1580, SED1590 Direct

LCD Controller → SED1750 Capacitor coupling is required SED1580, SED1590 → SED1750 Capacitor coupling is required SED1750 → SED1580, SED1590 Capacitor coupling is required

Cautions at Power Up and Power Down

Because the voltage level in the LCD system is high voltage, if the logic system power supply of this LSI is floating or if VCC is 2.6 V or less when the LCD system high voltage (30 V or above) is applied, or if the LCD drive signal is output before the voltage level that is applied to the LCD system has stabilized, then there is the risk that there will be an over current condition in this LSI, resulting in permanent damage to this LSI.

It is recommended that the display OFF function (DOFF) is used until the LCD system voltage stabilizes to insure that the LCD drive output power level is at the VC level.

Be sure to follow the sequences below when turning the power supplies ON and OFF:

When turning the power supply ON:

Logic system ON → LCD drive system ON, or simultaneously ON.

When turning the power supply OFF:

LCD drive system OFF → Logic system OFF, or simultaneously OFF.

As a countermeasure to guard against over current conditions, it is effective to insert a high-speed fuse or a guard resistance in series with the LC power supply. The guard resistance value must be optimized depending on the capacity of the LC cell.

CIO1 SHL SEL CSEL;

YD DOFF F1 F2 YSCL FR TEST1 CIO2

OSC3

OSC2

OSC1

COD0

COD1

COD2

COD3

COD4

LR1

LR0M/S

C86

SLEEP

XRESD0–7

WRRD

A0CS

CA

DOFF

F2

F1CL

FR160out

SED1750D0B

160out SED1590D0B VSSy

VDDx

VSSx CD0CD1CD2CD3CD4 VEE

VL

LP DOFF VL VEE SCI7500

POWER SUPPLY YDr VLCD

V3, V2, VC, –V2, –V3 VH, VC, VL, VDDY, VSSY

MPU I/F

160×160 DOT 1/160 DUTY

XDr VLCD XDr VLCD

Electric Volume Condenser

Coupling

Example of Connection