Unsere Ziele

(1)

14. November 2007 Theo Mustermann

Unsere Ziele

Das Forschungszentrum Jülich im Fokus

Mitglied der Helmholtz-Gemeinschaft

Detlev Grützmacher

Peter Grünberg Institut (PGI-9) Forschungszentrum Jülich

in collaboration with

CEA-LETI, MINATEC, 17 Rue des Martyrs, 38054 Grenoble Cedex 9, France

SOITEC, Parc Technologique des Fontaines, 38190 Bernin, France

Energy Efficient Transistors

(2)

Challenges in Nanoelectronics

strained Si

relaxed SiGe

1 nm

complex & expensive equipment scientific competence

excellent training and education

 interdisciplinarity

 broad material basis

 nanostructuring

 extensive nanoanalytics

 experiments on short/ultrashort time scales

Jülich Aachen Research

Alliance (JARA-FIT)

(3)

Peter Grünberg Institute (PGI-9) 3

INFORMATION

Jülich Aachen Research Alliance

– Fundamentals of Future Information Technology

28 Institutes of RWTH Aachen University and Forschungszentrum Jülich (11 FZJ; 17 RWTH) Contributing disciplines: Physics, Chemistry,

Electrical Engineering, Mechanical Engineering, Materials Science

Ernst-Ruska Center for Electron Microscopy - world leading facility jointly operated

Helmholtz Nanoelectronic Facility (under construction)

- leading cleam room facility for nanoelectronics

(4)

Why electronics goes „nano“ !

• Scaling 32/28/22 nm density performance more economic

• Future devices will be „fully depleted“

requires ultrathin layers ultrathin fins

nanowires: horizontal or vertical

• Nano enables

one dimensional physics

novel technologies e.g material tuning, core shell structures better electrostatic control of the devices

higher energy efficiency

• Major challenges

lithography

better materials needed variability

Gate

Si 6nm SiO2

Source Drain

OO.Weber et al. IEDM2010

(5)

Energy Efficiency Technology Driver

• Dynamic power dissipation

• Static power dissipation

(gate leakage and subthreshold leakage)

Most important levers to minimize power dissipation:

• Reduction of the supply voltage V _dd

• Decreasing the inverse subthreshold slope S < 60mV/dec

P _dyn ~ V ³

(6)

Lower V _dd Increase I _d !

Electrostatics

HfO ₂

Higher- k diel.:

LaLuO ₃

Scaling

≤ 22 nm Mobility

Access Resist.

Strained Si, sGe strained SiGe Silicide contacts

Device Design

FDSOI on UTB FinFET (NW)

How to improve switching?

Small slope switches: e.g. BTBT

(7)

Si - NW-Array Transistor

1000 parallel wires

NW cross-section: 20x20nm ² Gate oxide: 4nm SiO ₂ n-type Poly-Si gate

4nm

Si – Nanowire (NW)-Array Transistor

Si NW

poly-Si

SiO ₂

(8)

Ideal subthreshold swings, I _on /I _off ~ 10 ¹⁰

Output Characteristics <110> Transfer Characteristics <110>

20 x 20 nm ² NW Transistors Lg= 400 nm

S. Habicht et al. ESSDERC 2010

(9)

Fast switches Steep slope devices

0 Current

OFF ON

Ideal switch

I _on

-1,0 -0,5 0,0 0,5 1,0 1,5 2,0 10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

10

¹

I d (µ A/µm)

V _g (V)

OFF ON

V _dd

MOSFET

(10)

MOSFET vs. TFET

Thermal emission over potential barrier

Band-to-band

tunneling

(11)

How to increase BTBT current ?

 Improve electrostatic gate control, decrease λ



 High-k gate dielectric

) (

3 2 exp 4

~

g 2 3 g

WKB q E

E T m

I _ds



Source Drain Gate

Source

Drain Gate

 Decrease E _g and m*

 Tensile strained Si

 SiGe

 Heterostructures

λ : Screening length of electrical potential E

_g

: Bandgap

m*: Effective mass

(12)

• HfO ₂ , TiN gate stack

• ε _ox = 22

• Conformal deposition by ALD and AVD

High-k and metal gate

Nanowire array

2 µm gate

100 nm gate

(13)

• Best slope 76 mV/dec

• Average slope 97 mV/dec (10 ^-8 to 10 ^-4 µA/µm)

• Ambipolar characteristics

Transfer characteristics

Drain p⁺ Gate

Source n⁺

pTFET

V D < 0 V V _G < 0 V

V S = 0 V

Tunnel junction n

⁺

source to channel

S. Richter, Q.T. Zhao, S. Mantl et al., IEEE EDL submitted

(14)

SOI Si _0.5 Ge _0.5

Si i

HfO₂

TiN

p ⁺

n ⁺

Nanowire array

Source Drain

18 nm 10 nm

SiGe/Si nanowire heterostructure

Increased tunnel area for BTBT

SiGe

SOI

Free standing Si nanowire

(15)

Nanowires in Nanoelectronics: Examples

nanotransistor Single-electron

spin-qubit

spin-transistor

- phase coherence - spin transport important issues:

e 200nm

InN

(16)

Selective area growth

Metal-organic vapor phase epitaxy

(MOVPE)

InAs

Length: ~5µm

Diameter: ~100nm

(17)

Single Electron Tunneling

S D

back gate

S D

defect

(18)

Nanowires for Spin-Transistors?

500 nm

Gate fingers

Andreas Bringer , Th. S. (subm. PRB)

How does the spin precess in a ballistic

tubular system?

(19)

Topological Insulators

March 25th, 2011 slide 19

Graphene

Two opposite spin states form a single massless Dirac fermion and the crossing of their dispersion branches at a time-reversal invariant point is protected by the

time-reversal symmetry

HgCdTe/HgTe QW

König et.al.

J. Phys. Soc. Jpn.,77, 031007 (2008)

Quantum Spin Hall Effect

Bi ₂ Se ₃ , Bi ₂ Te ₃ and Sb ₂ Te ₃

Zhang et.al.

Nature Physics 5, 438 (2009)

(20)

MBE on Si (111) substrates

Quintuple layer by quintuple layer growth

0.0 0.5 1.0 1.5 2.0

-1 0 1

Height (nm)

Distance (µm)

0 10 20 30 40 50

Si(222)

Si(111) 00 21

00 18

00 15

006

Intensity (arb. units)

(degree)

single crystal Bi2Te3 crystal is (001)-oriented

003

Bright atoms: Bi

Dark atoms: Te

(21)

ARPES Scans

v _F = 3.05x10 ⁵ m/s

(22)

Our Research Value Chain

Si Nanowire CMOS Technology

Tunnel-FET (Ge => III/V compounds) III/V Nanowires and Spintronics

Topological Insulators

(Spintronics => Quantum Computation)

Today Tommorow

Beyond

(23)

Acknowledgement Team at PGI-9

EU Medea Project: „DECISIF“,

„KZWEI“

supported by

(24)

Unsere Ziele

14. November 2007 Theo Mustermann

Unsere Ziele

Das Forschungszentrum Jülich im Fokus

Detlev Grützmacher

Peter Grünberg Institut (PGI-9) Forschungszentrum Jülich

in collaboration with

CEA-LETI, MINATEC, 17 Rue des Martyrs, 38054 Grenoble Cedex 9, France

SOITEC, Parc Technologique des Fontaines, 38190 Bernin, France

Energy Efficient Transistors

Challenges in Nanoelectronics

complex & expensive equipment scientific competence

excellent training and education

 interdisciplinarity

 broad material basis

 nanostructuring

 extensive nanoanalytics

 experiments on short/ultrashort time scales

Jülich Aachen Research

Alliance (JARA-FIT)

INFORMATION

Jülich Aachen Research Alliance

– Fundamentals of Future Information Technology

28 Institutes of RWTH Aachen University and Forschungszentrum Jülich (11 FZJ; 17 RWTH) Contributing disciplines: Physics, Chemistry,

Electrical Engineering, Mechanical Engineering, Materials Science

Ernst-Ruska Center for Electron Microscopy - world leading facility jointly operated

Helmholtz Nanoelectronic Facility (under construction)

- leading cleam room facility for nanoelectronics

Why electronics goes „nano“ !

• Scaling 32/28/22 nm density performance more economic

• Future devices will be „fully depleted“

requires ultrathin layers ultrathin fins

nanowires: horizontal or vertical

• Nano enables

one dimensional physics

novel technologies e.g material tuning, core shell structures better electrostatic control of the devices

higher energy efficiency

• Major challenges

lithography

better materials needed variability

Gate

Si 6nm SiO2

Source Drain

OO.Weber et al. IEDM2010

Energy Efficiency Technology Driver

• Dynamic power dissipation

• Static power dissipation

(gate leakage and subthreshold leakage)

Most important levers to minimize power dissipation:

• Reduction of the supply voltage V dd

• Decreasing the inverse subthreshold slope S < 60mV/dec

P dyn ~ V 3

Lower V dd Increase I d !

Electrostatics

HfO 2

Higher- k diel.:

LaLuO 3

Scaling

≤ 22 nm Mobility

Access Resist.

Strained Si, sGe strained SiGe Silicide contacts

Device Design

FDSOI on UTB FinFET (NW)

How to improve switching?

Small slope switches: e.g. BTBT

Si - NW-Array Transistor

1000 parallel wires

NW cross-section: 20x20nm 2 Gate oxide: 4nm SiO 2 n-type Poly-Si gate

4nm

Si – Nanowire (NW)-Array Transistor

Si NW

poly-Si

SiO 2

Ideal subthreshold swings, I on /I off ~ 10 10

Output Characteristics <110> Transfer Characteristics <110>

20 x 20 nm 2 NW Transistors Lg= 400 nm

S. Habicht et al. ESSDERC 2010

Fast switches Steep slope devices

0

Current

• Reduction of the supply voltage V _dd

P _dyn ~ V ³

Lower V _dd Increase I _d !

HfO ₂

LaLuO ₃

NW cross-section: 20x20nm ² Gate oxide: 4nm SiO ₂ n-type Poly-Si gate

SiO ₂

Ideal subthreshold swings, I _on /I _off ~ 10 ¹⁰

20 x 20 nm ² NW Transistors Lg= 400 nm

I _on

V _g (V)

V _dd

I _ds

 Decrease E _g and m*

• HfO ₂ , TiN gate stack

• ε _ox = 22

• Average slope 97 mV/dec (10 ^-8 to 10 ^-4 µA/µm)

V D < 0 V V _G < 0 V

SOI Si _0.5 Ge _0.5

p ⁺

n ⁺