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iSBC® 546/547/548 HIGH PERFORMANCE TERMINAL CONTROLLERS HARDWARE REFERENCE MANUAL

Order Number: 122704-001

Copyright 1986, Intel Corporation, All Rights Reserved

I Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051 r

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Additional copies of this manual or other Intclliterature may be obtained from:

Literature Department Intel Corporation 3065 Bowers Avenue Santa Clara, CA 95051

The int(lrmation in this document is subject to change without notice.

Intel Corporation makes no warranty of any kind with regard to this material. including, but not limited to, the implied warranties of merchantability and fitne~s for a particular purpose. Intel Corporation assumes no respon~

sibility for any errors that may appear in this document. Intel Corporation makes no commitment to update nor to keep current the information contained in this dDcument.

Intel Corporation assumes no responsibility for the usc of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses arc implied.

Intel software products arc copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Inters software license. or as defined in ASPR 7~104.9(a)(9).

No part of this document may be copied or reproduced in any form or by any means without prior written consent of Intel Corporation.

Intel Corporation makes no warranty for the usc of its products and assumes no responsibility for any errors which may appear in this document nor docs it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice.

Contact your local sales office to ohtain the latest specifications bef()re placing your order.

The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products:

Above iLBX

BITBLJS im

COMMputer iMDDX

CREDIT iMMX

Data Pipeline lnsite

GENIUS Intel

-' inte l

i intclBOS

ICICE lntelcvision

ICE intc1igcnt Identifier

rCEL intcligent Programming

iCS lntcllec

iDBP Intcllink

iDIS iOSP

iPDS iPSC iRMX iSBC iSBX iSDM iSXM Library Manager MCS Megachassis MICROMAINFRAME MLJLTIBUS MULTICHANNEL MULTIMODULE

ONCE OpenNET

Plug~A~Bubblc

PROMPT Promware QucX QUEST Ripplcmodc RMX/SO RUPI Seamless SLD UPI VLSiCEL

MDS is an ordering code only and is not used as a product name or trademark. MDS" is a regi,tered trademark of Mohawk Data Sciences Corporation.

*MULTlBlJS is a patented Intel bus.

Copyright 1985, Intel Corporation, All Righb Reserved

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REV. REVISION HISTORY DATE

-001 Original Issue. 2/86

iii/tv

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(5)

PREFACE

This manual provides information about the iSBC 54B and iSBC 547 Eight Channel Terminal Controllers and the iSBC 546 Terminal and Printer Controller. The iSBC 548 and iSBC 547 boards are

functionally identical, but the iSBC 547 is a larger form factor (10" x 12") board with backpanel connectors on-board. The iSBC 546 is a four channel board with a clock calendar and a centronix printer interface.

General information about all three boards is provided in Chapter 1. Chapter 2 provides a block diagrams and functional descriptions of the boards. Chapter 3 provides the information required to

install the board. Programming information is provided in Chapter 4 as well as in Appendix A and B. Connector pin-out information for all boards is shown in Chapter 5. If you need to refer to the

schematic diagrams see Chapter 6.

For reference purposes Appendix A provides jumper information for the boards. Appendix B covers the board firmware.

In addition to this manual you will need the following reference material ( all are available from the Intel Literature Department, see page ii for address).

o Intel MULTIBUS Handbook, Order Number 210883

o Microsystem Components Handbook, Order Number 230843 o Serial Communications Controller Technical Manual,

Order Number 230834.

v

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(7)

CONTENTS ]

PAGE CHAPTER 1

GENERAL INFORMATION

1. 1 Introduction . . . " 1-1 1.2 Board Features . . . l-l 1.3 Board Description . . . 1-2 1.3.1 iSBC 546 Board Description . . . 1-2 1.3.2 iSBC 547 Board Description . . . 1-3 1.3.3 iSBC 548 Board Description . . . 1-3 1.4 Specifications . . . 1-8 CHAPTER 2

BOARD OPERATION

2 • 1 Introduction . . . " 2-1 2.2 iSBC 547 and iSBC 548 Functional Descriptions .. 2-l 2.3 iSBC 546 Functional Description . . . 2-4 CHAPTER 3

INSTALLATION

3 • 1 Introduction . . . 3-1 3.2 Unpacking And Inspection . . . 3-l 3.3 Compatible Equipment . . . • . . . 3-l 3.4 Installation Considerations . . . 3-2 3.4.1 Connector Configurations . . . 3-2 3.4.2 Battery Backup . . . 3-3 3.4.3 Cabling . . . 3-6 3.5 Installation Procedures . . . 3-9 CHAPTER 4

PROGRAMMING CONSIDERATIONS

4.1 Introduction . . . 4-1

4 • 2 Jumpers . . . 4-1 4.3 Addressing . . . 4-1 4.4 Programming Considerations . . . 4-3 4.4.1 Firmware . . . 4-3 4.4.2 80186 Processor Programming Considerations .... 4-3 4.4.3 8255 Programming . . . 4-6 4.4.4 DSR Port . . . 4-7 4.5 Baud Rate Programming (All Boards) . . . 4-7

vii

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CONTENTS (continued)

PAGE CHAPTER 5

INTERFACING INFORMATION

5.1 Introduction . . . . to • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 5-1 MULTI BUS Information . . . 5-1 5.2

5.3 5.4

serial Interfaces . . . 5-6 Printer InterfaCE~ (iSBC 546 Only) . . . 5-11 CHAPTER 6

SERVICE ASSISTANCE INFORMATION

6 -1 Introduction . . . 6-1 6-2 Service and Repair Assistance . . . 6-1 6-3 Service Diagrams . . . 6-3 APPENDIX A

JUMPER INFORMATION

A.1 Introduction . . . A-1 A.2 Flag Byte Address Jumpers . . . A-4 A.3 MULTIBUS Interrupt Jumpers . . . A-5 A.4 Memory Mapping Jumpers . . . A-5 APPENDIX B

FIRMWARE

B.1 Introduction . . . B-1 B.2 Firmware Overvie'iliT . . . B-1 B.2.1 Firmware Operation . . . B-4 B.2.2 Recommendations For High Performance . . . B-5 B.3 Functional Architecture . . . B-6 B.3.1 structures of Dual Ported RAM . . . B-6 B.3 . 1. 1 Test EnginE~ering Boot Area . . . B-7 B.3.1.2 static Structures . . . B-8 B.3.1.3 Dynamic Structures . . . B-10 B . 3 . 1 . 4 Queue. . . . . " . . . . . . . . . . . . . . . . B-1 0 B.3.1.5 Receive Buffers . . . B-11 B.3.1.6 Transmit Buffers . . . B-11 B.3.2 Inter-Processor Messages . . . B-11 B.3.2.l Host CPU to Controller Messages . . . B-ll B.3.2.1.1 Initialize . . . B-12 B.3.2.1.2

B.3.2.1.3 B.2.2.1.4 B.3.2.1.5 B.3.2.1.6 B.3.2.1.7 B.3.2.1.8

Enable .. ~I • • • • • • • • • • • • • • • • • • • • • • " • • • • • • • • • B-13 Disable. ~ . . . ' . . . B-14 Conf igurE~ . . . " . . . B-15 Transmit Buffer . . . B-20 Abort Transmit . . . B-2 2 Suspend Transmit . . . " . . . B-23 Resume Transmit . . . " . . . B-24

(9)

TABLEfJ (continued)

3-2 Pin to Pin Wiring List •...•...•..•.•...•.... 3-7 5-1 MULTI BUS Connector Pl Pin Assignments . . . • . . . . 5-l 5-2 MULTI BUS Connector Pl Signal Descriptions . . . 5-3 5-3 Connector P2 Pin Assignments . . . 5-5 5-4 Serial Connectors Pin Assignments, iSBC 546 . . . 5-6

Board

5-5 Serial Connectors Pin A!;signments, iSBC 547 . . . 5-7 Board

5-6 Serial Connectors Pin Assignments, iSBC 548 . . . 5-9 Board

5-7 Printer Interface Connec:::tor J5 Pin Assignments .... 5-ll 5-8 Connector J5 Signal Desc:::riptions . . . 5-12 A-l Jumper Combinations iSBC 546 Boards ...••... A-l A-2 Jumper Combinations iSBC 547/548 Boards . . . A-3 A-3 Flag Byte Address options And Jumpers . . . A-4 A-4 Memory Map jumpers and Addresses . . . A-6 B-1 iSBC 546/547/548 Firmware Features . . . B-2 B-2 Confidence Test Result Codes . . • . . . • . . . B-59

FIGUlRES

1-1 iSBC 546, iSBC 547 and iSBC 548 Boards . . . 1-5 Block Diagram

1-2 iSBC 548 High Performance Terminal Controller ... 1-6 1-3 iSBC 547 High Performance Terminal Controller ... 1-6 1-4 iSBC 548 High Performance Terminal Controller ... 1-7 2-1 iSBC 547 and iSBC 548 Functional Block Diagram.2-2 2-2 iSBC 546 Functional BLock Diagram . . . 2-6 3-1 iSBC 546 Board Connector Locations . . . 3-4 3-2 iSBC 547 Board Connector Locations . . . 3-5 3-3 iSBC 548 Board Connector Locations . . . 3-6 3-4 iSBC 548 RS232 Cable Construction . . . 3-8 4-1 iSBC 546/547/548 Boards Memory Map . . . 4-2 6-1 Territorial Service Telephone Numbers . . . 6-2 6-2 iSBC 548 Schematic Diagram . . . 6-4 6-3 iSBC 547 Schematic Diagram . . . 6-l5 6-4 iSBC 546 Schematic Diagram . . . 6-27 A-l iSBC 546 Board Jumper Location . . . A-7 A-2 iSBC 547 Board Jumper Location . . . A-8 A-3 iSBC 548 Board Jumper Location . . . A-9 B-1 Layout of Shared (Dual Port) Memory . . . B-6 B-2 Test Engineering Boot Area Layout . . . B-7 B-3 static Structure Area Layout . . . B-9 B-4 Dynamic Structure Layout . . . B-10 B-5 Layout of Queue Area . . . B-10 B-6 Initialize Message Format . . . B-12

x

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B-7 B-8 B-9 B-10 B-11 B-12 B-13 B-14 B-15 B-16 B-17 B-18 B-19 B-20 B-21 B-22 B-23 B-24 B-25 B-26 B-27 B-28 B-29 B-30 B-31 B-32 B-33 B-34 B-35 B-36 B-37 B-38 B-39

FIGURES (continued)

PAGE Enable Message F0rIl1at . . . " . . . B-13 Disable Message Format . . . " . . . B-14 Configure Message Pormat . . . " . . . B-15 Transmit Buffer Message Format . . . " . . . B-21 Abort Transmit Message Format . . . " . . . B-22 Suspend Transmit Message Format . . . " . . . B-23 Resume Transmit Message Format . . . " . . . B-24 Assert DTR Message Format •... " . . . B-25 Set CTS and CD GatE~s Message Format ... " . . . B-2 6 Clear CTS and CD Gates Message Format ... " . . . B-27 Set DSR Report Message Format . . . " . . . B-28 Clear DSR Report Message Format •... " . . . B-29 Set RI Report Message Format . . . ' ... B-3 0 Clear RI Report Message Format . . . ' ... B-31 Clear DTR Message Format . . . , ... B-32 Set Break Message Format . . . ' ... B-3 3 Clear Break Message Format . . . B-34 Download Message Format . . . ' ... B-3 7 Execute Command Message Format . . . B-38 Clear Receive Buffer Command Message Format ... B-40 Transmit Complete Message Format . . . B-41 Input Available message Format . . . B-43 Download Complete 'Message Format . . . B-44 Carrier Detect Message Format . . . B-45 Carrier Loss Message Format ...••.•... B-46 Initialization Responses Message Format . . . B-47 Autobaud Complete Message Format . . . B-48 Special Character Received Message Format . . . B-49 DSR Detected Message Format . . . B-50 DSR Lost Message Format . . . B-51 RI Detected Message Format . . . B-52 RI Lost Message Format . . . B-53 EPROM Checksum .... " . . . B-60

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CHAPTER 1 GENERAL INFORMATION

1.1 INTRODUCTION

The iSBC 548, iSBC 547 and iSBC 546 are three single board terminal controllers to be used in the MULTIBUS I environment. The iSBC 548 and iSBC 547 are eight channel controllers. The iSBC 546 has four channels plus a line printer i.nterface and clock/ca.lendar.

The purpose of this chapter is to introduce you to all three boards. The remaining chapters will provide more detailed

information on all the boards. This chapter gives a. list of the key features, a brief description of each board and a list of

specifications.

1.2 BOARD FEATURES

This section provides a brief list of key features of the iSBC 548 and iSBC 547 boards.

o Eight Mhz 80186 Microprocessors.

o Supports asynchronous RS232C interface in DTE configuration,on eight channels.

o 32K Byte dual-ported B~, 96K Byte local RAM and supports up to 64K Byte EPROM sites populated with :i:irmware (All Boards)

o Each serial channel supports transfer rates up to 19.2K Baud.

0 Up to 96K Baud (per board) throughput rate (Special Character or Tandem Mode not used)

0 Jumper selectable memory mapping

0 Jumper selectable I/O mapping

0 Jumper selectable MUL'l'IBUS interrupts

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GENERAL :rNl~ORMATION

o The iSBC 547 is a 10"x 12" form factor board with on-board backpanel connectors.

The iSBC 546 board differs from the iSBC 548 and iSBC 548 boards as follows:

o Four channels of RS232C instead of eight channels o Line printer interface

o Clock calendar with battery back-up

1.3 BOARD DESCRIPTIONS

sections 1.3.1, 1.3.2 and 1.3.3 provide general descriptions of the iSBC 548, iSBC 547 and iSBC 546 boards respectively. Figure 1-1 is a much simplified diagram for all three boards. Figures 1-2, 1-3 and 1-4 show the iSBC 548, iSBC 547 and iSBC 546 boards

respectively.

1.3.1 iSBC 548 BOARD DESCRIPTION

ThE: iSBC 548 board is a MULTIBUS based terminal con1:roller. The boa.rd communicates with a MULTIBUS host as a slave boa.rd.

The board uses an Intel 80186 microprocessor, operating at 8 Mhz as its

cpu.

The 80186 controls eight serial channels sending data to or receiving data from the MUL'TIBUS host. The on-board 80186 gains the attention of the MULTI BUS host by generating an interrupt over the MULTIBUS interface to the host. A flag byte mechanism allows the MULTIBUS host to interrupt the board, to reset thE! board, or to reset an interrupt to the MULTIBUS host generated by the board.

The: iSBC 548 board has four on-·board 82530 Serial Communications Controllers (SCC). Each 82530 SCC contains two on-chip baud rate generators, allowing each channE~l to be independently programmed for separate baud rates. The maximum baud rate per channel is 19.2K Baud. Two 40-pin connectors can be attached to IBM PCAT compatible 9-pin connectors via ribbon cable.

ThE! iSBC 548 board has four 64K x 4 DRAM (Dynamic RAM) devices, a total of 128 KBytes per board. The upper 32K Bytes can be addressed by other MULTIBUS boards.

J.-2

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GENERAL INFORMATION

The board also includes two 28-pin sockets. These sockets are populated with firmware EPROMs.

1.3.2 iSBC 547 BOARD DESCRIP'l~ION

The iSBC 547 board is a terminal controller expansion to the Intel system 320. The board communicates with a MULTIBUS host as a slave board.

The board uses an Intel 80186 microprocessor, operating at 8 Mhz as its CPU. The 80186 controls eight serial channels sending data to or receiving data from the MULTIBUS host. The on-board 80186 gains

t~e attention of the MULTI BUS host by generating an interrupt over the MULTIBUS interface to the host. A flag byte mechanism allows the MULTIBUS host to interrupt the board, to reset the board, or to reset an interrupt to the MULTIBUS host generated by the board.

The eight serial interfaces on the iSBC 547 board are through eight 9-pin connectors. The 9-pin connections are fully compatible with the IBM PCAT connections.

The iSBC 547 board has four on-~)oard 82530 Serial communications Controllers (SCC). Each 82530 sec contains two on-chip baud rate generators,allowing each channel to be independently programmed for separate baud rates. The maximum baud rate per channel is 19.2K Baud.

The iSBC 547 board has four 64K x 4 DRAM (Dynamic RAM) devices, a total of 128 KBytes per board. ~~he upper 32K Bytes can be addressed by other MULTIBUS boards.

The board also includes two 28-pin sockets. These sockets are populated with firmware EPROMs.

1.3.3 iSBC 546 BOARD DESCRIPTION

The iSBC 546 board is a terminal and line printer controller. The board communicates with a MULTIBUS host as a slave board.

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GENERAL INFORMATION

The board uses an Intel 80186 microprocessor, operating at 8 Mhz as

its

cpu.

The 80186 controls four serial channels, sending data to

or receiving data from the MULTIBUS host, and a line printer interface. The on-board 80186 ga.ins the attention of t.he MULTIBUS host by generating an interrupt over the MULTI BUS interface to the host. A flag byte mechanism allows the MULTIBUS host to interrupt the board, to reset the board, or to reset an interrupt to the MULTI BUS host generated by the l:Jioard.

The four serial interfaces on the iSBC 546 board are through four 9-pin connectors. The 9-pin connections are fully compatible with the IBM PCAT connections.

The line printer interface is compatible with the IBM line printer interface.

The iSBC 546 board has two on-board 82530 Serial Communications Controllers (SCC). Each 82530

sec

contains two on-chip baud rate generators,allowing each channel to be independently programmed for separate baud rates. The maximum baud rate per channel is 19.2K Baud.

The iSBC 546 board has four 64K x 4 DRAM (Dynamic RAJ~) devices, a total of 128 KBytes per board. The upper 32K Bytes can be addressed by other MULTIBUS boards.

The board also includes two 28-pin sockets. These sockets are populated with firmware EPROMs.

A clock/calendar circuit, unique to the iSBC 546, is backed up by a non-rechargeable battery which keeps the clock/calendar operating for six months with all other power off.

1-4

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RS232 INTERFACE CHLS 7 AND 8

(iSBC' 5471 548 ONLY)

, - - - -

RS232 INTERFACE CHlS 5 AND 6

(iSBe' 5471 548 ONLY)

PAINTER INTERFACE (iSBe 546 ONLY)

'"

I I

-

Figure 1-1.

GENERAL INFORMATION

5

- - -

REFRESH LOGIC (ALL BOARDS)

REFRESH CONTROL SIGNALS

MULTIBUS'

RAM (ALL BOARDS)

I RAM CONTROL SIGNALS

RAM CONTROL (ALL BOARDS)

80186 MICROPROCESSOR

(ALL BOARDS)

L __ _

CLOCK!

CALENDAR INTERFACE (iSBC' 546 ONLY)

iSBC 546, iSBC Block Diagram

ROM (ALL BOARDS)

547 and iSBC

r 3

2335

548 Boards,

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PIN 1

PIN2 TOP

BOTTOM

MULTIBUS' CONNECTOR P1

Figure 1-2. iSBC

Figure 1-3. iSBC

GENERAL INFORMATION

PIN 39 TOP PIN 40 BOTTOM SERIAL

CONNECTOR J1

PIN 1 TOP PIN2 BOTTOM

MULTIBUS' CONNECTOR P2

PIN 39 PIN 40 TOP BOTTOM SERIAL

CONNECTOR J2

548 High Performance Terminal Controller

547 High Performance Terminal Controller

1-6

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Figure 1-4. iSBC

GENERAL INFORMATION

PRINTER INTERFACE CONNECTOR

J5

MULTI BUS . CONNECTOR P1

SERIAL CONNECTOR

J4

/

SERIAL CONNECTOR

J3

/

SERIAL CONNECTOR

J2

/

MULTIBUS' GONNECTOR P2

548 High Performance Terminal Controller

2341

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GENERAL INFORMATION

1.4 SPECIFICATIONS

Table 1-1 summarizes the iSBC 546, iSBC 547 and iSBC 548 boards specifications.

Table 1-1. iSBC 546, iSBC 547, and iSBC 548 Specifications summary

Board Performance (Transfer Rate) iSBC 547 and iSBC 548 Boards

iSBC 546

Interfaces

iSBC 546 Board

1-8

Eight RS232C channels DTE configured. Maximum

transfer rate per channel 19.2K Baud. Typical

performance with :firmware is 96K Baud.

Four RS232C channels DTE configured. Maximum

transfer rate per channel 19.2K Baud.

MULTI BUS connectors PI and P2. All MUL'I'IBUS signals supported. The board at power-up requires an INIT pulse of at least 50

microseconds duration.

Four RS232C channels, four 9-pin connectors.

Line printer interface, one 25-pin connector.

Interface is compatible with IBM PC Line Printer interface with the

exception that. AU'rOFEED*

and SELECT-INPUT signals are not supported.

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GENERAL INFORMATION

Table 1-1. iSBC 546, iSBC S47, and iSBC 548 specifications Sumlllary (continued)

iSBC 547 Board

iSBC 548 Board

Electrical Requirements

+5.00V + 0.25V (Max. ) (Typ. ) +l2.00V + 0.60V (Max. ) (Typ. ) -12.00V + 0.60V (Max. ) (Typ. ) Environmental Characteristics

Temperature Humidity

MULTI BUS connectors PI and P2. All MULTIBUS signals supported. On power-up the board requires an INIT pulse of at least 50 microseconds duration.

Eight RS232C channels eight 9-pin connectors.

MULTI BUS connectors Pl and P2. All MULTIBUS signals supported. At power-up the board requires an INIT pulse of at least 50 microseconds duration.

Eight RS232C channels, two 40-pin connectors.

iSBC 546 iSBC 547 iSBC 548 3.260A 3.490A 3.490A

1. 700A 1. 870A 1. 870A 0.075A 0.l50A 0.150A 0.390A 0.082A 0.082A 0.069A 0.l38A 0.138A 0.041 0.082A 0.082A

o

to 55 degrees C, minimum, 200 LFM of airflow

5% to 90%, non-condensing (25 to 55 degrees C)

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GENERAL INFORMATION

Table 1-1. iSBC 546, iSBC 547, and iSBC 548 specifications Summary (continued)

Physical Dimensions

width

Length

iSBC 546 1:2.00 in (30.48 cm)

10.00 in (25.40 cm) Height (Including Components) 0.50 in

( 1. 27 cm)

1-10

iSBC 547 iSBC 548 12.00 in 12.00 in (30.48 cm) (30.48 cm)

10,,00 in 7.00 in (25.40 cm) (17.78 cm)

0.50 in 0.50 in ( 1. 27 cm) ( 1. 27 cm)

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2.1 INTRODUCTION

CHAPTER 2 BOARD OPERATION

This chapter describes the operation of the three controller

boards, the iSBC 546, the iSBC 547, and the iSBC 548. The iSBC 547 and iSBC 548 boards are functionally identical and their operation will be described jointly. The iSBC 546 board will be considered separately.

2.2 iSBC 547 AND iSBC 548 FUNCTIONAL DESCRIPTIONS

Figure 2-1 is a block diagram for the iSBC 547 and iSBC 548

boards. The boards are functionally identical and differ only in dimensions and in the type and number of serial interface

connectors (eight 9-pin connectors for the iSBC 547 and two 40-pin connectors for the iSBC 548).

The iSBC 547 and iSBC 548 boards can not address the MULTIBUS interface, both are slave boards only. The interface to the

~ruLTIBUS is through edge connectors PI and P2.

30th boards use an Intel 80186 microprocessor, operating at 8 Mhz as their main processors. The 80186 has a 16 bit data bus and 16 bit internal architecture. The 80186 provides all bus controls without the need of a separate bus controller device.

'rhe 80186 on the iSBC 547/548 controls eight serial channels sending data ,through them, from the MULTIBUS host or receiving data, through them, to the MUL'l~IBUS host. Data transfer to and from the MULTIBUS is by use of a 32K Byte communication table

(shared dual port memory) in the on-board dual-port RAM. The

HULTIBUS host informs the on-bc)ard 80186 which serial channels are enabled. The 80186 then polls those channels continuously, looking for data from the MULTIBUS host, or the need to supply data to the HULTIBUS host.

The structure of the communication table is described in Appendix B, section B.3.1 of this manual. The main blocks in the

communication table in the on-board RAM are: a command queue (dynamic structures area), a status queue (static structures

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CHANNEL 8

CHANNEL 4

CHANNEL 2

RS23~1

CHANNEL CKT

NOTE:

ISBC' 547 AND ISBC" 548 ARE FUNCTIONALLY IDENTICAL THE EIGHT SERIAL CHANNELS OF THF Isac" 547 ARE- BROUGHT our THROUGH 8 PIN CONNECTORS THE EIGHT SERIAL CHANNELS OF THE ISSC' 548 ARE BROUGHT OUT THROUGH TWO 40·PIN CONNECTORS

Figure 2-1.

IOB~·IOB7

I/O BUFFER

iSBC

BOARD OPERATION

80186 PROCESSOR

C ______

M_V_L,T,',B_V_S_' __ _ _ ----<J

SELMBL, HOST

, - - - -

REFREQ REFRESH

LOGIC

o~-o15 A1·A8

·:---1

,-~~---- , - - - ' " ' - - - - ,

RAM CONTROL AND ARBITRATION

LOGIC

RAS',eM,'

- - - -

WRLWRH'

- - -

AD'

ENLCL, ENLCH, LDCOEN AAM 128 K BYTES

~-~-l

- '~=-l-"" F~==-d j

,.---"'-=~·I [I"'"'' -=' .

L---,JJ

I 2338

547 and iSBC 548 Functicmal Block Diagram

2-2

(24)

BOARD OPERATION

a~ea), a transmission area (transmit buffers), and a set of

rE:!cei ve buffers. The MULTIBUS host gains the attention of the on- board 80186 to the command queUE! by a flag byte interrupt. The on- board 80186 gains the attention of the MULTIBUS host to the status queue by generating an interrupt over the MULTIBUS interface to the host. The interrupt line is jumper selectable as shown in Table A-2.

T::1e flag byte mechanism allows the MULTIBUS host to interrupt the controller board, to reset the board, or to reset an interrupt to t::le MULTIBUS host generated by the board. The flag byte

interrupt, sent by the MULTIBUS host to the controller board is an eige triggered input to the interrupt line of the on-board 80186.

The flag byte is mapped to I/O space at a jumper selectable

a::idress (see Appendix A , Table A-2 of this manual). Interrupting tile MULTIBUS host is done by writing data to an I/O port addressed through PCS5* (asterisk indicates signal is active low).

Ea.ch of the controller boards include two 28-pin sockets which are populated by two Intel 2764 EPROMs which contain the controller

firmware. Appendix B of this manual describes the firmware in

dl:~tail.

Although the controller boards are supplied with 2764 EPROMs the boards can support 27128 and 27256 EPROMs as well. The EPROM runs with zero wait states. The optional EPROMs must have access times

o:E 250 ns or less. No jumper changes need be made when the different size EPROMs are used.

Each of the boards has four 64K x 4 DRAMs (Dynamic RAMs), a total of 128K Bytes of on-board RAM. ~rhe upper 32K Bytes of the on-board RAM can be addressed by other MULTI BUS boards as well as the on- b::>ard processor. The dual-port HAM can be seen from the MULTIBUS at several different starting addresses. The starting addresses are jumper selectable (see Table A-3 in Appendix A of this

manual). The RAM operates with :z:ero wait states.

'Il:1e RAM is controlled with a PAL (Programmable Array Logic)

device. The PAL generates all signals needed to control the RAM, arbitrate between the MULTIBUS host, the refresh logic and the 80186 and enables the address lbuffers as required. The on-board H .. hl1 is selected by the LCS (Lowler Chip Select) signal generated by the on-board 80186. The memory arbiter allows refresh of the RAM even when the memory is locked.

(25)

BOARD OPERATION

RAM refresh uses a 1 Mhz output from Timer 1 of the on-board

80186. A divide by 15 counter causes a refresh request to be sent to the PAL arbiter every 15 microseconds. An eight bit counter addresses the RAM.

The serial channels of the controller boards are implemented in flour 82530 Serial Communication Controller (SCC) chips. The baud rate clock for the serial channels is generated by the 82530 secs. Each channel has its own two on-chip baud rate generators, allowing each channel to be programmed separately. Chapter 4 of this manual describes baud rate programming.

The 82530 SCCs are selected by the PCSl* (Peripheral Chip Select) through PCS4* outputs of the on-board 80186. The DSR signals from the RS232 serial connectors are all tied to one input port decoded by the PCSo* line of the 80186.

2.3 iSBC 546 FUNCTIONAL DESCRIPTION

The iSBC 546 board, Figure 2-2, is similar to both the iSBC 547 and 548 boards. It differs primarily in that it has a line printer interface connector and associated circuitry, a clock/calendar circuit and supports only four serial channels.

The iSBC 546 processes data in the same manner as the other two boards; it has the same on-board RAM and controls it in same way as the other boards. The serial channels are controlled in the same manner as on the iSBC 547/548 boards except only two 82530 SCC devices are used.

The line printer interface is implemented through port A of an 8255A Programmable Peripheral Interfa,ce (PPI operated in strobed output mode). A PAL device controls timing and the line printer.

Approximately two microseconds after data is written to port A the PAL generates a LP STB* (Line Printer Strobe) signal to the printer indicating data to the printer is valid. LP STB* stays active for one microsecond. When LP ACK (Line Printer

Acknowledge) is returned by the printer it clears the port and allows more data to be sent.

The 8255A PPI is selected by the PCS3* signal generated by the on- board 80186. The PPI replaces one of the SCC devices in the I/O map for the controller boards.

2-4

(26)

BOARD OPERATION

The interface does not have RS2:32 lines 5 through 8, freeing four bits of the DSR port. These four lines are used for line printer status lines LP BUSY (Line Printer Busy), NO PAPER, FAULT and LP SELECT (Line Printer Select).

The line printer interface is compatible with the IBM line printer interface and with proper cabling interfaces to a Centronix line printer.

rrhe clock calendar circuit uses a MM58167 clock chip and a 32.768 KHz crystal. The interface to the MM58167 uses the same PAL device as does the line printer interface. Port B of the 8255A device is used in both input or output strobed mode. PC4* and PC5* generated by the 8255A inform the PAL of either input or output mode.

Coding of the two bits is as follows:

Function PC4* PC5*

Output to Clock Mode 1 0 Input From Clock Mode 0 1

Reset LP and Clock 1 1

Interface

Reset Clock Interface 0 0 Only

1;'1henever a new clock set is issued or a clock read is started PC4 * ,.3.nd PC5* must be reset to 0,0 and the port set to the appropriate ::node, input or output. Then PC~~* and PC5* are programmed to the

correct logic level and the hardware supplies the address to the clock by order, starting from milliseconds and all the way up to 'the clock internal RAM area. Only the first 16 addresses in the clock chip are addressable.

'rhe PAL generates the control ~;ignals for the 8255A PPI. The data sent to the clock or received from the clock consists of eleven ::.')ytes.

'rhe clock/calendar is backed-up by a non-rechargeable battery 'ilhich insures at least six months operation with no off-board power. The battery back-up is ~iumper selectable.

(27)

PRINTER CONNECTOR

CHANNEL 4 LOAlO·

LDAT7, OSR5·0SRs

TRANSCEIVER

Figure 2-2.

IOBP-9

BOARD OPERATION

PROGRAMMABLE PERIPHERAL

INTERFACE 10BO- IOB7

ClKBUSO- CLKBUS7

CLOCK AND CALENDER

CKT

110

BUFFER 'r---

ADO-AD?

80186 PROCESSOR

ADO-.I\.015

' - - - -

~

(~

SELMBL, HOS T

REFRESH

~

LOGIC

RAS·. CAS'

r---

AAMCONTROL AND ARBITRATION

LOGIC WRl', WRH'

~

LOC DEW

1

ADO-AD15

:::)

BUFFERS RAM

MUlTiBUS"

t)

AORO-.IORF

~ DATO-CIATF

MULTIBUS" BUFFER

]

Ii

Al-AB

U

00-015

RAM 128K BYTES

i

00-015 ~

2336

iSBC 546 Board Functional Block Diagram

2-6

(28)

3.1 INTRODUCTION

CHAPTER 3 INSTALLATION

This chapter explains how to receive, inspect and then install the.

iSBC 548, iSBC 547 and iSBC 546 boards. However, before

installation you should read Chapter 4 Programming Considerations and Appendix A Jumper Information. Once you have set up the jumpers according to your system requirements proceed with the installation procedures in this chapter.

3.2 UNPACKING AND INSPECTION

Inspect the shipping carton immediately upon receipt for evidence of mishandling during transit. If the shipping carton is damaged or water stained, request the carrier's agent be present when the

carton is opened. If the carrier's agent is not present when the carton is opened and the contents are damaged, keep the carton and packing material for the agents inspection.

United states customers can obtain service and repair assistance by contacting the Intel product service hotline in Phoenix, Arizona

(see Chapter 6 for more information). customers outside the United states should contact their sales source (Intel sales office or authorized distributor) for service information and repair

assistance.

3.3 COMPATIBLE EQUIPMENT

The iSBC 548 can be installed in any MULTIBUS Compatible chassis.

The iSBC 547 board serves as a terminal controller expansion to the Intel System 320.

The iSBC 546 is part of the basic Intel System 320.

(29)

INSTALLATION

3.4 INSTALLATION CONSIDERATIONS

The following sections describe some of the installation consideration for the three boards.

THe iSBC 548, 547, and 546 boards can be configured to reside in 32 different address locations (see Table A-4) in the MULTIBUS address space. The board's flag byte address (wake-up address) is jumper selectable (see Table A-3) with eight options available in the

MULTIBUS address space. The iSBC 548 and iS4H In the most ideal mult each controller board (iSBC 548, 547 or 546) would have different I/O mapping, different memory mapping and different .interrupt

lines. Under these conditions up to eight controller boards can be used in a system.

In a system application where more than eight controller boards are required the boards are grouped so that several boards share the same I/O address and the same interrupt line. The boards however cannot share the same address space.

As an example, if a system has one unused interrupt line, two unused I/O address lines, in the 8AO through 8A7 range, and 20 unused address locations in the range the controller boards can be configured to (see Table A-4), than 20 different controller boards can be installed in the system. The boards will share the same interrupt line and use either one or two I/O addresses.

3.4.1 CONNECTOR CONFIGURATIONS

On all three boards connectors PI and P2 are the MULTIBUS

connectors. Pin assignments for each connector are provided in Table 5-1 and Table 5-3 respectively. The location of each connector on each board is shown in Figures 3-1, 3-2, and 3-3.

Table 5-1 and Table 5-3 respectively.

On the iSBC 548 board connectors Jl and J2 are the serial I/O connectors (see Table 5-6 for pin assignments).

3-2

(30)

INSTALLATION

On the iSBC 547 board connectors Jl through J8 are the serial I/O connectors (see Table 5-5 for pin assignments) .

On the iSBC 546 board connectors Jl through J4 are the serial I/O connectors (see Table 5-4 for pin assignments). connector J5 is the printer interface connector (see Table 5-7 for pin assignments and Table 5-8 for signal descriptions).

3.4.2 BATTERY BACKUP

In order to use the battery backup for the clock/calendar on the iSBC 546 board the jumper between E30 and E3l must be installed by the user. In the default condition (as delivered from the factory) the backup battery is installed but the jumper is not.

(31)

PIN 1 TOP PIN2 BOTTOM

MULTIBUS®

CONNECTOR P1

Figure 3-1.

PIN 39 TOP PIN 40 BOTTOM

iSBC

INSTALLATION

PIN 1 TOP PIN2 SERIAL

CONNECTOR J1 BOTTOM

MULTIBUS@

CONNECTOR P2

PIN 39 TOP PIN 40 BOTTOM

548 Board Connector Locations

3-4

SERIAL CONNECTOR J2

2339

(32)

Figure 3-2.

MULTIBUS®

CONNECTOR Pl

iSBC

INSTALLATION

SERIAL CIHANNEL CONNECTORS

MULTIBUS~

CONNECTOR P2

547 Board Connector Locations

2342

(33)

Figure 3-3. iSBC

3.4.3 CABLING

INSTALLATION

PRINTER INTERFACE CONNECTOR

J5

MULTIBUS®

CONNECTOR Pl

SERIAL CONNECTOR

J4

/

SERIAL CONNECTOR

J3

/

SERIAL CONNECTOR

J2

/

MULTIBUS®

CONNECTOR P2

546 Board Connector Locations

2341

The iSBC 548 board requires two flat 40 conductor cables to connect to the back panel. These cables can be acquired from Intel as part of the Intel 310 Cable Kit or can be fabricated by the user. Table 3-1 summarizes the recommended cable and connector part numbers for the iSBC 548 board. Figure 3-4 shows the cable construction.

Table 3-2 lists the pin to pin wiring for the cable shown in Figure 3-4.

3-6

(34)

INSTALLATION

The iSBC 546 and iSBC 547 boards do not require cables. Connection is made directly on the card edge.

Table 3-1. Recommended Cables and Connectors Connector

40 Pin or 40 Pin or 40 Pin or 40 Pin

9 Pin

Manufacturer Part Number

3M 3417··6000 (without strain relief) 3M 3417-6040 (with strain relief) T&B Ansley 609-4000M (without strain relief) T&B Ansley 609-400lM (with strain relief T&B Ansley 609-9P-ML (metal shroud, male)

Table 3-2. Pin to Pin wiring List 40 Pin P4 P3 40 Pin P2 P1

Connector Connector

1 5

-

19 5

-

2 9

-

20 9

-

3 4

-

21 4

-

4 8

-

22 8

-

5 3

-

23 3

-

6 7

-

24 7

-

7 2

-

25 2

-

8 6

-

26 6

-

9 1

-

27 1

-

10

-

5 28

-

5

11

-

9 29

-

9

12

-

4 30

-

4

13

-

8 31

-

8

14

-

3 32

-

3

15

-

7 33

-

7

16

-

2 34

-

2

17

-

6 35

-

6

18

-

1 36

-

1

P1ns 37 through 40 of 40 p1n connector not used. P1 through P4 are 9-pin connectors.

(35)

iSBC® 548 COMPONENT SIDE

INSTALLATION

EACH 9 CONDUCTOR LENGTH IS 5 INCHES

LAST FOUR PINS OPEN

40 PIN MALE CONNECTOR

r---~-5

BOTTOM

2334

Figure 3-4. iSBC 548 RS232C Cable Construction

3-8

(36)

INSTALLATION

3.5 INSTALLATION PROCEDURE

The following is a general procedure for installing the terminal controller boards.

1. Check Appendix A for the jumper configuration.

2. Ensure that power to your system is turned off.

3. For the iSBC 548 board install the I/O cables to the 40 pin connectors.

4. Install the terminal controller board into the appropriate slot in your cardcage. Ensure that connectors Pl and P2 are fully seated in the cardcage.

(37)
(38)

4.1 INTRODUCTION

CHAPTER 4 PROGRAMMING CONSIDERATIONS

This chapter describes the programming considerations applicable to the users of the iSBC 546, iSBC 547 and iSBC 548 boards. This

information can be used by a user wishing to run his own software on the boards, using the download feature.

4.2 JUMPERS

Appendix A of this manual locates the various jumpers (for all three controller boards) and describes their functions. The user should reference this appendix to verify that the required jumpers have been installed by the factory (the default condition) or to

install his own configuration.

4.3 ADDRESSING

Figure 4-1 is a memory map for the iSBC 546/547/548 controllers.

The controller boards include two 28 pin sockets that can support either 2764, 27128 or 27256 EPROMs. Decoding of this memory portion is done by the 80185 processors UCS (Upper Chip Select) signal.

Because of the different EPROMs capacities the starting addresses for this memory portion will vary as follows:

EPROM 2764 27128 27256

Memory Size 16K 32K 64K

Starting Address FCOOO(H) F8000(H) FOOOO(H)

There are four 64K x 4 DRAMS on each controller board, a total of 128K Bytes. The upper 32K Bytes can be addressed by other MULTIBUS

(39)

PROGRAMMING INFORMATION BOIB6

Microprocessor OFFFFF(H) ~-===

__

~

UCS FCOOO(H),

2764 EPROM/

FBOOO(H), 2712B EPROM/

FOOOO (H), / 27256 EPROM

64K Bytes

LCS 12BK Bytes

On-Board Memory

16/32~64

K Bytes

EPROM

64K Bytes Dual Port

RAM

RAM

MULTI BUS FFBOOO(H)

-:..- - - - -

32K Bytes

' - - - -

FSOOOO(H) OFFFFF (H)

I

r:,.- - - - -

32K Bytes - - - - - -

OSOOOO(H) ~ ______ ~ NOTE

Dual-ported RAM can be accessed on the MULTIBUS between SOOOO(H) and FSOOO(H) or FBOOOO(H) and FFBOOO(H) on any 32K boundary.

Figure 4-1. iSBC 546/547/548 Boards Memory Map 4-2

(40)

PROGRAMMING CONSIDERATIONS

master boards. The dual-ported RAM can be addressed from the MULTIBUS interface at any 32K boundary starting between 80000(H) and F8000(H) or between F80000 and FF8000. The starting address is jumper determined see Appendix A). For the iSBC 546 board the

default starting address is OFAOOOO(H). For the iSBC 547 and 548 boards the default starting address is OF90000(H).

4.4 PROGRAMMING CONSIDERATIONS

sections 4.4.1 through 4.4.3 discuss the programming considerations for the three controller boards

4.4.1 FIRMWARE

The firmware for the controller boards is described in detail in Appendix B of this manual. The following paragraphs provide a brief description of firmware operation.

The 80186 microprocessors on the iSBC 547 and iSBC 548 boards control eight serial data channels. The 80186 on the iSBC 546 controls four serial data channels. The data received from the channel is communicated to the MULTI BUS host and the data

transmitted to the channel is received from the MULTIBUS host. The MULTIBUS host informs the controller's 80186 which channels to enable and which not. The 80186 continuously polls the enabled channels looking for data or the request for data.

On the iSBC 546 board the line printer channel and clock/calendar are treated like serial channels.

4.4.2 80186 PROCESSOR PROGRAMMING CONSIDERATIONS

When programming the controller's 80186 microprocessor the following guidelines should be followed:

1. The LCS (Lower Chip Select) should be programmed for 128K Byte size and zero wait states.

(41)

PROGRAMMING CONSIDER1!.TIONS

2. The UCS (Upper Chip Select) should be programmed for 64K Byte size and zero wait states.

3. The PCS (Peripheral Chip Select) should be I/O mapped and configured as follows:

PCS

o

1 2 3

4

5

Function

Selects DSR port. PCSO is not to to be used for for an output.

Selects serial ports 1 and 2.

Selects serial ports 3 and 4.

Selects serial ports 5 and 6 on iSBC 547 and 548 boards and line printer interface and

clock/calendar on the iSBC 546 board.

Selects serial ports 7 and 8 (iSBC 547 and 548 only)

sets MULTI BUS interrupt port when used as an output. PCS5 is not to be used as an input.

One wait state: should be used for the PCS lines.

If the PCS lines base address is O(H) then the I/O map will be as follows:

Address Port Type

0000 0000 OXXX XXXX DSR Port I

0000 0000 1XXX XOOO Serial Line 2, I/O

control

0000 0000 1XXX X010 Serial Line 2, I/O

data

0000 0000 1XXX X100 Serial Line 1, I/O

control

0000 0000 1XXX X110 Serial Line 1, I/O

data

4-4

(42)

PROGRAMMING CONSIDERATIONS

0000 0001 OXXX XOOO 0000 0001 OXXX XOIO 0000 0001 OXXX XIOO 0000 0001 OXXX XIIO 0000 0001 lXXX XOOO

0000 0001 lXXX XOIO

0000 0001 lXXX XIOO

0000 0001 lXXX XIIO 0000 0010 OXXX XOOO 0000 0010 OXXX XOIO 0000 0010 OXXX 0100 0000 0010 OXXX 0110 0000 0010 lXXX XXXX

serial Line 4, I/O control

Serial Line 4, I/O data

Serial Line 3, I/O control

Serial Line 3, I/O data

Serial Line 6,

control or I/O

Line Printer 0 serial Line 6, I/O data or

clock/calendar

Serial Line 5, I/O control or Line

Printer and clock/

calendar controls

Serial Line 5 data I/O or 8255 control 0 Serial Line 8, I/O control

Serial Line 8, I/O data

Serial Line 7, I/O control

Serial Line 7, I/O data

MULTI BUS Interrupt 0 In the RAM case EXTERNAL RDY overrides INTERNAL RDY. If INTERNAL RDY is active but EXTERNAL RDY is not, a wait state must be inserted.

The A2 address line selects between serial channels on the same components. When A2 equals

a

the port with the larger number is selected.

(43)

4.4.3

PROGRAMMING CONSIDERATIONS

The 80186 address mapping I/O should be programmed as follows:

Port

UMCS (Upper Memory Chip Select) LMCS (Lower Memory Chip Select) PACS (Peripheral Chip Select) MPCS (Mid-Range Peripheral Chip Select)

Address OFFAO(H}

OFFA2(H) OFFA4(H) OFFA8(H)

Data OF038(H) IFF8(H) 0039(H) 80B9 (H) 4. Timer 1 is programmed for a 1 Mhz output. Its mode

control (I/O address 5E(H» should be written with OC003(H) and the count register (I/O address 5A(H»

should be written with 00001(H).

5. The interrupt controller should have only one external interrupt. INTI from the flag byte activates interrupt 13 routine.

Except for software interrupts there are only two timer interrupts available, timers 0 and 2 can be used by the firmware.

8255 PROGRAMMING

Programming considerations for the 8255 Programmable Peripheral Interface (PPI) are as follows:

The 8255 PPI control word (address 186(H» should be programmed OA4(H) when the clock is to be set, and OA6(H) when the clock is to be read. To set PC4 and PC5 to desired levels, single bit

addressing should be used.

To determine if data from the clock is available bit 0 of the input port 184(H) should be checked. If bit 0 is 1 data is available.

To determine if the clock or line printer are ready for more data, port 184(H) bits 0 (for clock) and 3 (for line printer) should be read. A 1 for either bit indicate a readiness for more data.

4-6

(44)

PROGRAMMING CONSIDERATIONS

4.4.4 DSR PORT

The DSR port control word format for each controller board is shown below:

D7 D6 D5 D4 D3 D2 Dl DO

Line No Llne

Fault Printer Paper Printer DSR4 DSR3 DSR2 DSRI

Select Busy

lSBC 546 Board

D7 D6 D5 D4 D3 D2 Dl DO

DSR8 DSR7

I

DSR6

I DS~5 I

DSR4

I

DSR3 DSR2 DSRI

lSBC 547 and lSBC 548 Boards

4.5 BAUD RATE PROGRAMMING (ALL BOARDS)

To program the baud rate of a specific channel a time constant must be written to its time constant register. The time constant is calculated as follows:

Clock

Time Constant

=

- 2

---=-=-~-=~---

32 X Baud Rate Where: Clock

=

4.9152 Mhz

Baud rates and their corresponding time constants are as follows:

Baud Rate Time Constant (Decimal)

19,200 6

9,600 14

4,800 30

2,400 62

1,200 126

600 254

300 510

(45)
(46)

5.1 INTRODUCTION

CHAPTER 5 INTERFACING INFORMATION

This chapter provides pin assignments for all connector interfaces of the iSBC 546, iSBC 547 and iSBC 548 boards.

5.2 MULTIBUS INFORMATION

All three boards connect to the MULTI BUS interface through board connectors PI and P2. Table 5-1 lists MULTIBUS connector PI pin assignments, Table 5-2 describes the functions of the PI signals.

Table 5-3 lists MULTIBUS connector P2 pin assignments.

Table 5-1. MULTIBUS Connector P1 Pin Assignments

(Component Side) (Circuit Side)

Pin Mneumonic Description Pin Mnemonic Description

I GND Signal GND 2 GND Signal GND

3 +5V +5 Vdc 4 +5V +5 Vdc

5 +5V +5 Vdc 6 +5V +5 Vdc

7 +12V +12 Vdc 8 +12V +12 Vdc

9 Reserved 10 Reserved

11 GND Signal GND 12 GND Signal GND

13 14 INIT Initialize

15 16

17 18

19 MRDC* Mem Read Cmd 20 MWTC* Mem Write Cmd

21 22 IOWC* I/O Write Cmd

23 XACK* XFER Ack 24 INHl* ~nhibit I

25 LOCK* Bus Lock 26 Reserved

27 BHEN* Byte High En 28 ADRI0*

29 30 ADRll* Address Bus

31 32 ADR12*

33 34 ADR13*

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